Flash memory device and a method of fabrication thereof
View Patent ↗In a first aspect of the present invention, a method of fabricating a flash memory device is disclosed. The method comprises the steps of providing a portion of a dual gate oxide in a periphery area of the memory device and then simultaneously providing a dual gate oxide in a core area of the memory device and completing the dual gate oxide in the periphery area. Finally, a nitridation process is provided in both the core and periphery areas subsequent to the previous steps. In a second aspect of the present invention, a flash memory device is disclosed. The flash memory device comprises core area having a plurality of memory transistors comprising an oxide layer, a first poly layer, an interpoly dielectric layer, and a second poly layer. The flash memory device further comprises a periphery area having a plurality of transistors comprising an oxide layer, a portion of the first poly layer, and the second poly layer. According to the present invention, the method for fabricating the flash memory device is a simplified process that results in a significant improvement in the oxide reliability in the core and periphery areas and also eliminates the nitrogen contamination problem in the periphery area.
1. A method for fabricating a memory device on a silicon substrate, the method comprising the steps of:
(a) providing a portion of a dual gate oxide in a periphery area of the memory device;
(b) simultaneously providing a dual gate oxide in a core area of the memory device and completing the dual gate oxide in the periphery area, wherein the dual gate oxide in the core area forms an interface between the oxide and the silicon substrate;
(c) strengthening the interface by providing a nitrification process in both the core area and periphery area of the memory device subsequent to steps (a) and (b), thereby improving the reliability of the dual gate oxide in the core area;
(d) depositing a layer of type-1 polysilicon in both the core area and periphery area of the memory device;
(e) depositing a layer of oxide nitride oxide over the layer of type-1 polysilicon; and
(f) removing the layer of oxide nitride oxide and a portion of the layer of type-1 polysilicon from the periphery area of the memory device, wherein step (f) further includes removing approximately half the layer of type-1 polysilicon from the periphery area of the memory device.
2. The method of claim 1 further comprising:
(g) depositing a layer of type-2 polysilicon in both the core and periphery areas of the memory area.
3. A method for fabricating a memory device on a silicon substrate, the method comprising the steps of:
(a) providing a portion of a dual gate oxide in a periphery area of the memory device;
(b) simultaneously providing a dual gate oxide in a core area of the memory device and completing the dual gate oxide in the periphery area, wherein the dual gate oxide in the core area forms an interface between the oxide and the silicon substrate;
(c) strengthening the interface by providing a nitrification process in both the core area and periphery area of the memory device subsequent to steps (a) and (b), thereby improving the reliability of the dual gate oxide in the core area;
(d) depositing a layer of type-1 polysilicon in both the core area and periphery area of the memory device;
(e) depositing a layer of oxide nitride oxide over the layer of type-1 polysilicon; and
(f) removing the layer of oxide nitride oxide and a portion of the layer of type-1 polysilicon from the periphery area of the memory device.
4. A method for fabricating a memory device on a silicon substrate, the method comprising the steps of:
(a) providing a portion of a dual gate oxide in a periphery area of the memory device;
(b) simultaneously providing a dual gate oxide in a core area of the memory device and completing the dual gate oxide in the periphery area, wherein the dual gate oxide in the core area forms an interface between the oxide and the silicon substrate; and
(c) strengthening the interface by providing a nitrification process in both the core area and periphery area of the memory device subsequent to steps (a) and (b), thereby improving the reliability of the dual gate oxide in the core area;
(d) depositing a layer of type-1 polysilicon in both the core area and periphery area of the memory device;
(e) depositing a layer of oxide nitride oxide over the layer of type-1 polysilicon; and
(f) removing the layer of oxide nitride oxide and a portion of the layer of type-1 polysilicon from the periphery area of the memory device.