IP Library Granted Patent US 6,861,267
Granted Patent B2
US 6,861,267 · App. 09/953,833 · Granted Mar 1, 2005

Reducing shunts in memories with phase-change material

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Quick Facts
Patent No.
US 6,861,267
App. No.
09/953,833
Granted
Mar 1, 2005
Kind
B2
Abstract

A memory cell may include a phase-change material. Adhesion between the phase-change material and a dielectric or other substrate may be enhanced by using an adhesion enhancing interfacial layer. Conduction past the phase-change material through the interfacial layer may be reduced by providing a discontinuity or other feature that reduces or prevents conduction along said interfacial layer.

Claims (26)

1. A method comprising:

forming a passage through a dielectric layer;

covering said passage with an adhesion promoting material;

creating an electrical discontinuity in said adhesion promoting material along said passage; and

forming a phase-change material in said passage.

2. The method of claim 1 including forming a dielectric layer over a contact layer and forming said passage through said dielectric layer to said contact layer.

3. The method of claim 2 including covering said passage with an adhesion promoting material that is conductive.

4. The method of claim 1 wherein creating an electrical discontinuity includes forming an opening in said adhesion promoting material.

5. The method of claim 4 wherein forming a passage includes forming a dielectric having at least two discrete layers and forming the passage through said layers.

6. The method of claim 5 including forming a substantially vertically extending passage through said layers and then forming a lateral extension in said passage into one of said layers.

7. The method of claim 6 including forming said lateral extension by selectively isotropically etching one of said layers.

8. The method of claim 7 wherein forming a passage includes forming a dielectric with three layers including a middle layer.

9. The method of claim 8 including selectively isotropically etching the middle layer of said three layers.

10. A method comprising:

forming a passage through a dielectric layer;

covering said passage with a conductive material;

preventing conduction along said passage via said conductive material; and

forming a phase-change material in said passage.

11. The method of claim 10 including forming a dielectric layer over a contact layer and forming said passage through said dielectric layer to said contact layer.

12. The method of claim 11 including covering said passage with a conductive material that promotes adhesion between said phase-change material and said dielectric layer.

13. The method of claim 10 wherein preventing conduction along said passage via said conductive material includes creating an electrical discontinuity in said conductive material along said passage.

14. The method of claim 13 wherein forming a passage includes forming a dielectric having at least two discrete layers and forming said passage through said layers.

15. The method of claim 14 including forming a substantially vertically extending passage through said layers and then forming a lateral extension in said passage in one of said layers.

16. The method of claim 15 including forming said lateral extension by selectively isotropically etching one of said layers.

17. The method of claim 16 wherein forming said passage includes forming a dielectric with three layers including a middle layer.

18. The method of claim 17 including selectively isotropically etching the middle layer of said three layers.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2012
From: INTEL CORPORATION
To: NUMONYX B.V.
Reel/Frame 028055/0625 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027075/0682 →