IP Library Granted Patent US 6,882,546
Granted Patent B2
US 6,882,546 · App. 09/970,749 · Granted Apr 19, 2005

Multiple die interconnect system

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Quick Facts
Patent No.
US 6,882,546
App. No.
09/970,749
Granted
Apr 19, 2005
Kind
B2
Abstract

A multiple integrated circuit (IC) die assembly includes a base IC die and secondary IC dice mounted on a surface of the base IC die. A set of protruding contacts formed on the surface of the base IC die and extending beyond the secondary IC dice link the surface of the base IC die to a printed circuit board (PCB) substrate with the secondary IC die residing between the base IC die and the PCB substrate.

Claims (30)

1. A multiple die electronic system comprising:

a substrate having conductors formed thereon,

a base IC die having a first surface facing the substrate and a second surface parallel to the first surface,

a first secondary IC die residing between the first surface of the base IC die and the substrate and linked to the first surface of the base IC die through first conductive signal paths,

conductive contacts extending between the first surface of the base IC die and the conductors on the substrate for conveying first signals between the base IC die and the conductors on the substrate, wherein at least one of second signals provided between the first secondary IC die and the base IC die has a higher frequency than the first signals provided between the base IC die and the substrate.

2. The multiple die electronic system in accordance with claim 1 wherein solder forms the first conductive signal paths.

3. The multiple die electronic system in accordance with claim 1 wherein the substrate is a printed circuit board substrate.

4. The multiple die electronic system in accordance with claim 1 wherein the substrate is a semiconductor substrate.

5. The multiple die electronic system in accordance with claim 1 wherein the conductive contacts comprise resilient spring contacts.

6. The multiple die electronic system in accordance with claim 1 wherein the conductive contacts comprise:

resilient spring contacts formed on the first surface of the base IC die, and a spring contact socket providing signal paths between the spring contacts and the conductors on the substrate.

7. The multiple die electronic system in accordance with claim 1 further comprising:

a third level IC die residing between the first surface of the base IC die and a third surface of the first secondary IC die residing between the first surface of the base IC die and the substrate, the third level IC linked to the third surface of the second level IC die through conductive signal paths.

8. The multiple die electronic system in accordance with claim 5 wherein the spring contacts are formed an the first surface of the base IC die and soldered to the conductors on the substrate.

9. A multiple die electronic comprising:

a substrate having conductors formed thereon:

a base IC die having a first surface facing the substrate and a second surface parallel to the first surface;

a first secondary IC die residing between the first surface of the base IC die and the substrate and linked to the first surface of the base IC die through first conductive signal paths;

conductive contacts comprising resilient springs extending between the first surface of the base IC die and the conductors on the substrate for conveying signals between the base IC die and the conductors on the substrate; and

means for holding the base IC die proximate to the substrate so that the spring contacts are compressed against the conductors on the surface of the substrate.

10. A multiple die electronic comprising:

a substrate having conductors formed thereon;

a base IC die having a first surface facing the substrate and a second surface parallel to the first surface;

a first secondary IC die residing between the first surface of the base IC die and the substrate and linked to the first surface of the base IC die through first conductive signal paths;

first conductive contacts extending between the first surface of the base IC die and the conductors on the substrate for conveying signals between the base IC die and the conductors on the substrate;

a second secondary IC die; and

second conductive paths linking the second secondary IC die to the second surface of the base IC die.

11. The multiple die electronic system in accordance with claim 10 further comprising:

conductive vias for providing signal paths between the first and second surfaces of the base IC die.

12. The multiple die electronic system in accordance with claim 10 wherein the second conductive paths comprise spring contacts.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Aug 7, 2025
From: HSBC BANK USA, NATIONAL ASSOCIATION
To: FORMFACTOR, INC.
Reel/Frame 072853/0001 →
SECURITY INTEREST Recorded Jul 29, 2025
From: FORMFACTOR, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
Reel/Frame 072263/0272 →
SECURITY INTEREST IN UNITED STATES PATENTS AND TRADEMARKS Recorded Jul 12, 2016
From: FORMFACTOR, INC.; ASTRIA SEMICONDUCTOR HOLDINGS, INC.; CASCADE MICROTECH, INC.; MICRO-PROBE INCORPORATED
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 039184/0280 →