Data processor assigning the same operation code to multiple operations
View Patent ↗A data processor can assign a greater number of operations to instruction codes with shorter length, thereby implementing high performance, high code efficiency and low cost data processor. The data processor is a VLIW (Very Long Instruction Word) system that can execute a plurality of operations in parallel, and specify the execution sequence of the operations. It can assign a plurality of operations to the same operation code, and the operations that are executed in a second or subsequent sequence are limited to only predetermined operations among the plurality of operations.
1. A data processor for processing an instruction that includes a first operation code field, a second operation code field, and an execution sequence specifying field for specifying an execution sequence of a plurality of operations specified by a plurality of operation code fields including the first operation code field and the second operation code field, said data processor comprising:
instruction decoding means for decoding instructions; and
instruction executing means for executing the instructions according to a decoded result by said instruction decoding means, wherein said instruction decoding means includes:
first decoding means for decoding the first operation code field when an operation specified by the first operation code field is executed in a first execution sequence in accordance with a content specified by the execution sequence specifying field;
second decoding means for decoding the second operation code field when an operation specified by the second operation code field is executed in the first execution sequence in accordance with the content specified by the execution sequence specifying field; and
decision means for making a decision as to which one of decoding means including said first decoding means and said second decoding means is to be used for decoding the operation code field to be executed in a second or subsequent execution sequence in accordance with the content specified by the execution sequence specifying field, and
wherein said instruction executing means comprises:
means for executing a first operation in response to the decoded result by said first decoding means when the first operation code field has a first bit pattern, and when the operation specified by the first operation code field is executed in the first execution sequence according to the execution sequence specifying field; and
means for executing a second operation different from the first operation in response to the decoded result by said second decoding means when the second operation code field has the first bit pattern, and when the operation specified by the second operation code field is executed in the first execution sequence according to the execution sequence specifying field.
2. The data processor according to claim 1 , wherein said instruction executing means further comprises:
means for executing the second operation in response to the decoded result by said second decoding means when the first operation code field has the first bit pattern, when the execution sequence specifying field specifies that the operation specified by the first operation code field is to be executed in the second or subsequent execution sequence, and when said decision means makes a decision that said second decoding means is used for decoding the first operation code field.
3. The data processor according to claim 2 , wherein said decision means makes a decision in response to a decoded result by a decoder other than said first decoding means and said second decoding means.
4. The data processor according to claim 2 , wherein said decision means makes a decision in response to decoded results by decoders including said first decoding means and said second decoding means.