IP Library Granted Patent US 6,847,282
Granted Patent B2
US 6,847,282 · App. 09/981,993 · Granted Jan 25, 2005

Multiple layer inductor and method of making the same

Assignee: Broadcom Corporation
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Quick Facts
Patent No.
US 6,847,282
App. No.
09/981,993
Granted
Jan 25, 2005
Kind
B2
Abstract

A multiple layer inductor has a first spiral conductive pattern disposed on a first surface; a second spiral conductive pattern disposed on a second surface; a continuing interconnection coupled to the first and second spiral conductive patterns; an interface coupled to the first and second spiral conductive patterns; and a conductive shield pattern disposed on a third surface that is adjacent to the second surface. The interface includes a first terminal disposed on the first surface that is coupled to the first spiral conductive pattern. The interface also includes a second terminal that is disposed on the first surface and coupled to said second spiral conductive pattern.

Claims (26)

1. A multiple layer inductor implemented on a substrate having a plurality of layers, each layer having a top surface and a bottom surface, said multiple layer inductor comprising:

a first spiral conductive pattern disposed on a top surface of a first of the plurality of layers;

a second spiral conductive pattern disposed on a top surface of a second of the plurality of layers;

a continuing interconnection coupled to said first and second spiral conductive patterns;

an interface having a first terminal and a second terminal disposed on said top surface of said first of the plurality of layers, wherein said first terminal is coupled to said first spiral conductive pattern and second terminal is coupled to said second spiral conductive pattern;

a first conductive shield pattern having a first common voltage potential and disposed on a top surface of a third of the plurality of layers, wherein said third of the plurality of layers is adjacent to said second of the plurality of layers; and

a second conductive shield pattern having a second common voltage potential and disposed on a top surface of a fourth of the plurality of layers, wherein said fourth of the plurality of layers is adjacent to said top surface of said first of the plurality of layers;

first and second conductive side shield patterns disposed on respective perimeters of said first and second layers.

2. The multiple layer inductor of claim 1 , wherein said continuing interconnection comprises:

a first via coupled to said first and second spiral conductive patterns; and

a second via coupled to said second spiral conductive pattern and said second terminal.

3. The multiple layer inductor of claim 1 , wherein said continuing interconnection comprises:

a first via coupled to said first spiral conductive pattern;

a second via coupled to said second spiral conductive pattern;

a third spiral conductive pattern disposed on a fourth surface that is coupled to said first and second vias.

4. The multiple layer inductor of claim 3 , wherein said first and second spiral conductive patterns have a first orientation, and wherein said third spiral conductive pattern has a second orientation that is different than said first orientation.

5. The multiple layer inductor of claim 1 , wherein said continuing interconnection comprises:

a first via coupled to said first spiral conductive pattern;

a second via coupled to said second spiral conductive pattern; and

a plurality of coupled of spiral conductive patterns, each disposed on a respective one of a plurality of adjacent layers;

wherein a first of the plurality of spiral conductive patterns is coupled to said first via, and a second of the plurality of spiral conductive patterns is coupled to said second via.

6. The multiple layer inductor of claim 5 , wherein said plurality of coupled of spiral conductive patterns have orientations that alternate according to adjacent surfaces.

7. The multiple layer inductor of claim 1 , wherein said first and second spiral conductive patterns have different orientations.

8. The multiple layer inductor of claim 7 , wherein said first and second shield patterns are grounded.

9. The multiple layer inductor of claim 1 , further comprising first and second conductive side shield patterns disposed on said first and second layers, respectively.

10. The multiple layer inductor of claim 9 , wherein said first and second side shield patterns are grounded.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2001
From: GOMEZ, RAMON A.; BURNS, LAWRENCE M.
To: BROADCOM CORPORATION
Reel/Frame 012282/0437 →
Continuity (1)
Related Publication 20030076210A1 · Apr 24, 2003