Semiconductor device having impurity region under isolation region
View Patent ↗In formation of a source/drain region of an NMOS transistor, a gate-directional extension region < 41 a > of an N + block region < 41 > in an N + block resist film < 51 > prevents a well region < 11 > located under the gate-directional extension region < 41 a > from implantation of an N-type impurity. A high resistance forming region, which is the well region < 11 > having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode < 9 >, can be formed as a high resistance forming region <A 2 > narrower than a conventional high resistance forming region <A 1 >. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
1. A semiconductor device having an SOI structure formed by a semiconductor substrate < 1 >, an embedded insulating layer < 2 > and an SOI layer < 3 >, comprising:
a plurality of element forming regions provided in said SOI layer, each formed with a prescribed element;
an isolation film < 31 > provided in an upper layer part of said SOI layer for isolating said plurality of element forming regions from each other;
a first conductivity type semiconductor region < 11 , 12 > provided under said isolation film as part of said SOI layer, said semiconductor region being formed in contact with at least one of said plurality of element forming regions having a first conductivity type among said plurality of element forming regions; and
a first conductivity type body region < 10 > provided in said SOI layer and capable of being externally fixed in electric potential, said body region being in contact with said semiconductor region, wherein
said semiconductor region at least partially has a first conductivity type impurity region not mixed with an impurity of a second conductivity type different from said first conductivity type but doped by only an impurity of said first conductivity type.
2. The semiconductor device according to claim 1 , wherein
said first conductivity type impurity region is formed in a region < 36 > reaching said at least one element forming region from said body region.
3. The semiconductor device according to claim 1 , wherein
said isolation film at least partially has a second conductivity type impurity-free region containing no impurity of said second conductivity type.
4. The semiconductor device according to claim 3 , wherein
said second conductivity type impurity-free region is formed in a region reaching said at least one element forming region from said body region.
5. The semiconductor device according to claim 3 , wherein
said second conductivity type impurity-free region includes a region having a larger thickness than the remaining region in said isolation film.
6. The semiconductor device according to claim 1 , wherein
said prescribed element includes a transistor, and a gate electrode < 9 > of said transistor is formed to extend on said isolation film.
7. The semiconductor device according to claim 1 , wherein
a dummy region < 73 , 74 > formed in said SOI layer not to function as an element.
8. The semiconductor device according to claim 7 , wherein
said dummy region includes a region where impurities of both of said first conductivity type and said second conductivity type are introduced.
9. The semiconductor device according to claim 7 , wherein
said dummy region includes a first dummy region< 72 > where an impurity of said first conductivity type is implanted and no impurity of said second conductivity type is implanted and a second dummy region < 71 > where an impurity of said second conductivity type is implanted and no impurity of said first conductivity type is implanted.