Granted Patent
Utility
US 6,779,144
· Confirmation No. 4513
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF TESTING IT
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2004-05-12 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2001-11-30 | TRNA |
Transmittal of New Application | 4 | View | |
| 2001-11-30 | SPEC |
Specification | 40 | View | |
| 2001-11-30 | CLM |
Claims | 6 | View | |
| 2001-11-30 | ABST |
Abstract | 1 | View | |
| 2001-11-30 | DRW |
Drawings-only black and white line drawings | 10 | View | |
| 2001-11-30 | OATH |
Oath or Declaration filed | 4 | View |
Inventors
Attorneys & Agents of Record
Classification
USPC
714/731
Prosecution
- Examiner
- TON, DAVID
- Art Unit
- 2133
- Customer No.
- 181
- Docket No.
- XA-9588
- Confirmation No.
- 4513
Foreign Priority
2000-371585
·
2000-12-06
·
JAPAN
Publication
- Pub. No.
- US20020069382A1
- Pub. Date
- 2002-06-06
Patent Term Adjustment
0days
No related applications found.
CHANGE OF ADDRESS
Recorded 2017-11-29
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2014-05-09
from
HITACHI, LTD.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2003-12-11
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2001-11-30
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Quick Facts
- Patent No.
- US 6,779,144
- App. No.
- 09/996,722
- Filed
- 2001-11-30
- Granted
- 2004-08-17
- Pub. No.
- US20020069382A1
- Examiner
- TON, DAVID
- Art Unit
- 2133
- PTA
- 0 days
External Links