IP Library Granted Patent US 6,846,149
Granted Patent B2
US 6,846,149 · App. 09/996,869 · Granted Jan 25, 2005

Semiconductor wafer processing system with vertically-stacked process chambers and single-axis dual-wafer transfer system

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Quick Facts
Patent No.
US 6,846,149
App. No.
09/996,869
Granted
Jan 25, 2005
Kind
B2
Abstract

A semiconductor wafer processing system including a multi-chamber module having vertically-stacked semiconductor wafer process chambers and a loadlock chamber dedicated to each semiconductor wafer process chamber. Each process chamber includes a chuck for holding a wafer during wafer processing. The multi-chamber modules may be oriented in a linear array. The system further includes an apparatus having a dual-wafer single-axis transfer arm including a monolithic arm pivotally mounted within said loadlock chamber about a single pivot axis. The apparatus is adapted to carry two wafers, one unprocessed and one processed, simultaneously between the loadlock chamber and the process chamber. A method utilizing the disclosed system is also provided.

Claims (9)

1. A semiconductor wafer process apparatus comprising:

a dual-wafer single-axis transfer arm adapted to carry and transfer semiconductor wafers between a loadlock chamber and a semiconductor wafer process chamber, said transfer arm having a monolithic arm pivotally mounted within said loadlock chamber about a single pivot axis;

wherein said transfer arm is adapted to carry at least two wafers simultaneously between said loadlock chamber and said process chamber; and

wherein said transfer arm comprises a retracted home position and an extended position in which said transfer arm extends into said process chamber, wherein said single pivot axis allows said transfer arm to pivot between said retracted and extended positions.

2. The semiconductor wafer process apparatus according to claim 1 further comprising a cooling plate disposed below said transfer arm when said pivot arm is in said retracted position.

3. The semiconductor wafer process apparatus according to claim 2 wherein said cooling plate further comprises a plurality of lift pins for transporting the wafers between said cooling plate and said transfer arm.

4. The semiconductor wafer process apparatus according to claim 1 wherein the transfer arm comprises an end effector, said effector comprising an upper shelf and a lower shelf with wafer edge supports thereon respectively and being coupled to the monolithic transfer arm, said effector pivoting with the monolithic arm about said pivot axis.

5. A semiconductor wafer process apparatus according to claim 1 wherein said transfer arm further comprises a lower wafer shelf for carrying a processed wafer and an upper wafer shelf for carrying an unprocessed wafer.

6. A semiconductor wafer processing apparatus according to claim 1 wherein said transfer arm is adopted to simultaneously carry one unprocessed wafer and one processed wafer.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Jul 5, 2016
From: JPMORGAN CHASE BANK, N.A.
To: SPTS TECHNOLOGIES LIMITED
Reel/Frame 039257/0026 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2015
From: JPMORGAN CHASE BANK, N.A.
To: SPTS TECHNOLOGIES LIMITED
Reel/Frame 036558/0351 →
SECURITY INTEREST Recorded Apr 2, 2015
From: SPTS TECHNOLOGIES LIMITED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 035364/0295 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded May 9, 2007
From: AVIZA TECHNOLOGY, INC.; AVIZA, INC.
To: UNITED COMMERCIAL BANK
Reel/Frame 019265/0381 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2004
From: ASML US, INC.
To: THERMAL ACQUISITION CORP.
Reel/Frame 015633/0412 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2004
From: THERMAL ACQUISITION CORP.
To: AVIZA TECHNOLOGY, INC.
Reel/Frame 015636/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2003
From: SAVAGE, RICHARD N.; MENAGH, FRANK S.; CARVALHEIRA, HELDER R.; TROIANI, PHILIP A.; COSSENTINE, DAN L.; VAUGHN, ERIC R.; MAYER, BRUCE E.
To: ASML US, INC.
Reel/Frame 013739/0153 →