Method and apparatus for configuration control and power management through special signaling
View Patent ↗A method and apparatus for configuration control and power management through special signaling is provided. In one embodiment, a computer system may include a processor and a plurality of devices that may act as a source device, a destination device, or both. A particular source device may be configured for communications with a destination device. The source device may further be configured to violate one or more known communications rules when communicating the with the destination device. The destination device may be configured to detect the violation. The violation of a known communications rule by the source device may indicate a pending change of state in the computer system, or that a change of state has occurred.
1. A system comprising:
a source device;
a destination device coupled to the source device;
wherein the source device is configured to violate a known communications rule, and wherein the destination device is configured to detect said violating a known communications rule, and wherein the destination device includes a phase locked loop (PLL);
wherein said violating a known communications rule indicates to the destination device a change in the state of the system, and wherein said violating comprises the source device driving a clock signal to the destination device at a frequency that is outside of a specified frequency range, and wherein the PLL is configured to detect said driving a clock signal outside of the specified frequency range.
2. The system as recited in claim 1 , wherein said violating indicates a command from the source device to the destination device to change the state of the system.
3. The system as recited in claim 1 , wherein said violating provides an indication from the source device to the destination device that a change in the state of the system has occurred.
4. The system as recited in claim 1 , wherein said violating comprises driving signals from an input pin of the source device, and wherein the destination device is configured to detect said driving.
5. The system as recited in claim 1 , wherein the system is a computer system, the computer system comprising:
a processor;
an input/output (I/O) controller coupled to the processor;
a peripheral bus coupled to the I/O controller; and
at least one peripheral device coupled to the peripheral bus.
6. The system as recited in claim 5 , wherein the computer system comprises a docking station and a mobile unit.
7. The system as recited in claim 6 , wherein said violating indicates that the mobile unit is to be undocked from the docking station.
8. The system as recited in claim 5 , wherein the peripheral device is a plug-and-play peripheral device.
9. The system as recited in claim 8 , wherein said violating indicates that the peripheral device is to be removed from the system.
10. The system as recited in claim 8 , wherein said violating indicates that the peripheral device has been inserted into the system.
11. The system as recited in claim 5 , wherein said violating indicates that the peripheral device has been inactive for a predetermined period of time.
12. A method comprising:
a source device communicating with a destination device;
the source device violating a known communications rule;
the destination device detecting said violating, wherein said detecting indicates to the destination device a change of state of a system comprising the source device and the destination device, and
detecting said violating with a phase-locked loop (PLL), wherein the PLL is comprised by the destination device, wherein said violating comprises the source device driving a clock signal to the destination device at a frequency that is outside of a specified frequency range, and wherein the PLL is configured to detect said driving a clock signal outside of the specified frequency range.
13. The method as recited in claim 12 , wherein said violating indicates a command from the source device to the destination device to change the state of the system.
14. The method as recited in claim 12 , wherein said violating provides an indication from the source device to the destination device that a change in the state of the system has occurred.
15. The method as recited in claim 12 , wherein said violating comprises driving signals from an input pin of the source device, wherein the destination device is configured to detect said driving.
16. The method as recited in claim 12 , wherein the system comprising the source device and the destination device is a computer system, the computer system comprising:
a processor;
an input/output (I/O) controller coupled to the processor;
a peripheral bus coupled to the I/O controller; and
at least on peripheral device coupled to the peripheral bus.
17. The method as recited in claim 16 , wherein the computer system comprises a docking station and a mobile unit.
18. The method as recited in claim 17 , wherein said violating indicates that the mobile unit is to be undocked from the docking station.
19. The method as recited in claim 16 , wherein the peripheral device is a plug-and-play peripheral device.
20. The method as recited in claim 19 , wherein said violating indicates that the peripheral device is to be removed from the system.
21. The method as recited in claim 19 , wherein said violating indicates that the peripheral device has been inserted into the system.
22. The method as recited in claim 16 , wherein said violating indicates that the peripheral device has been inactive for a predetermined period of time.
23. A system comprising:
a source device;
a destination device coupled to the source device;
wherein the source device is configured to violate a known communications rule, and wherein the destination device is configured to detect said violating a known communications rule, and wherein the destination device includes a phase locked loop (PLL);
wherein said violating comprises the source device changing the frequency of a clock signal by a specified amount, wherein the PLL is configured to detect said violating by detecting said changing the frequency.
24. A system comprising
a source device;
a destination device coupled to the source device;
wherein the source device is configured to violate a known communications rule, and wherein the destination device is configured to detect said violating a known communications rule, and wherein the destination device includes a phase locked loop (PLL), and wherein said violating comprises the source device transmitting a frequency modulated signal to the destination device, and wherein the destination device is configured to detect the frequency modulated signal.
25. A system comprising:
a source device;
a destination device coupled to the source device;
wherein the source device is configured to violate a known communications rule, and wherein the destination device is configured to detect said violating a known communications rule;
wherein said violating a known communications rule indicates to the destination device a change in the state of the system, and wherein said violating comprises the source device transmitting a combination of clock signals and data signals to the destination device, wherein the combination is in violation of a standard encoding.