IP Library Granted Patent US 7,018,878
Granted Patent B2
US 7,018,878 · App. 10/045,653 · Granted Mar 28, 2006

Metal structures for integrated circuits and methods for making the same

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Quick Facts
Patent No.
US 7,018,878
App. No.
10/045,653
Granted
Mar 28, 2006
Kind
B2
Abstract

Metal structures for ICs and methods for manufacturing the same are described. The metal structures range from small features to large features and are resistant to peeling problems during heat treatments that occur during the manufacturing process. Peeling of the metal structures from the underlying structures or substrates is reduced or prevented. The peeling problems are reduced or prevented by including a capping layer or capping structure over the dielectric layer over the metal structure and then annealing the capping layer or capping structure, thereby enhancing the adhesion of the metal structure to the underlying structure or substrate.

Claims (40)

1. A method for making a semiconductor device, comprising:

providing a metal structure comprising tungsten on a substrate;

providing an insulating layer over the metal structure;

providing a capping structure over the insulating layer; and

annealing the resulting structure, wherein a portion of the metal structure has a width greater than about 1 micron, wherein the capping structure and annealing prevents peeling of the metal structure when heated.

2. The method of claim 1 , wherein the substrate comprises a dielectric upper surface.

3. The method of claim 1 , the capping structure comprising a substantially continuous layer.

4. The method of claim 1 , the capping structure comprising a dielectric material.

5. The method of claim 4 , wherein the dielectric material of the capping structure is PSG.

6. The method of claim 1 , including planarizing the insulating layer before providing the capping structure.

7. The method of claim 1 , including annealing for about 30 to about 60 minutes at a temperature ranging from about 675 to about 700 degrees Celsius.

8. A method for making a semiconductor device, comprising:

providing a metal structure on a substrate, the metal structure comprising tungsten and a portion of the metal structure having a width greater than about 1 micron; and

providing an insulating layer over the metal structure;

providing a capping structure over the insulating layer; and

annealing the resulting structure;

wherein the capping structure and annealing prevents peeling of the metal structure when heated.

9. A method for making a semiconductor device, comprising:

providing a metal structure on a substrate, the metal structure comprising tungsten and a portion of the metal structure having a width greater than about 1 micron; and

providing an insulating layer over the metal structure;

providing a capping structure over the insulating layer; and

annealing the resulting structure;

wherein the annealing prevents peeling of the metal structure when heated.

10. A method for preventing peeling of a metal structure in a semiconductor device, comprising:

providing a metal structure comprising tungsten on a substrate;

providing an insulating layer over the metal structure;

providing a capping structure over the insulating layer; and

annealing the resulting structure, wherein a portion of the metal structure has a width greater than about 1 micron, and wherein the annealing prevents peeling of the metal structure when heated.

11. A method for preventing peeling of a metal structure in a semiconductor device, comprising:

providing a metal structure on a substrate, the metal structure comprising tungsten and a portion of the metal structure having a width greater than about 1 micron; and

providing an insulating layer over the metal structure;

providing a capping structure over the insulating layer; and

annealing the resulting structure;

wherein the annealing prevents peeling of the metal structure when heated.

12. A semiconductor device made by the method comprising:

providing a metal structure on a substrate, the metal structure comprising tungsten and a portion of the metal structure having a width greater than about 1 micron; and

providing an insulating layer over the metal structure;

providing a capping structure over the insulating layer; and

annealing the resulting structure;

wherein the capping structure and annealing prevents peeling of the metal structure when heated.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2016
From: SANDISK 3D LLC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038845/0372 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →