Semiconductor device structure and method for forming
A semiconductor device structure has trenches of two widths or more. The smallest widths are to maximize density. The greater widths may be required because of more demanding isolation, for example, in the case of non-volatile memories. These more demanding, wider isolation trenches are lined with a high quality grown oxide as part of the process for achieving the desired result of high quality isolation. For the case of the narrowest trenches, the additional liner causes the aspect ratio, the ratio of the depth of the trench to the width of the trench, to increase. Subsequent deposition of insulating material to fill the trenches with the highest aspect ratios can result in voids that can ultimately result in degraded yields. These voids are avoided by etching at least a portion of the liners of those trenches with the highest aspect ratios to reduce the aspect ratio to acceptable levels.
1. A method for forming a semiconductor device structure in a semiconductor layer, comprising:
forming a first trench of a first width and a second trench of a second width in the semiconductor layer;
growing a first insulator liner in the first trench and a second insulator liner in the second trench;
forming a mask over the second trench;
etching at least a portion of the first insulator liner while the mask is over the second trench;
removing the mask; and
depositing an insulating layer in the first trench and the second trench.
2. The method of claim 1 , wherein the first width is less than the second width.
3. The method of claim 1 , wherein the step of etching comprises completely removing the first insulator liner.
4. The method of claim 1 , wherein the step of etching results in leaving at least one hundred Angstroms of the first insulator liner.
5. The method of claim 1 , wherein the step of growing the first insulator liner and the second insulator liner comprises growing oxide in the first trench and the second trench.
6. The method of claim 1 , wherein the step of etching comprises dipping the semiconductor device structure in hydrofluoric acid.
7. The method of claim 1 , wherein the step of etching comprises applying a dry etch chemistry to the semiconductor device structure.
8. The method of claim 1 , wherein the insulator layer comprises high density plasma oxide fill.
9. The method of claim 1 , further comprising forming a barrier layer and a stress relief layer over the semiconductor layer in areas adjacent to the first trench and the second trench.
10. The method of claim 1 , further comprising forming a pad nitride and pad oxide over the semiconductor layer prior to forming the first trench and the second trench, and wherein the step of forming the first trench and the second trench comprises etching through selected portions of the pad nitride and the pad oxide and into the semiconductor layer.
11. A method for forming a semiconductor device structure in a semiconductor layer, comprising:
forming a first trench of a first width and a second trench of a second width in the semiconductor layer, the first width being less than the second width;
growing a first insulator liner in the first trench and a second insulator liner in the second trench;
forming a mask over the second trench; and
etching at least a portion of the first insulator liner while the mask is over the second trench.
12. The method of claim 11 , wherein the step of etching comprises a wet etch.
13. The method of claim 12 , wherein the step of etching comprises dipping the semiconductor device structure in hydrofluoric acid.
14. The method of claim 11 , wherein the etching comprises a dry etch.
15. The method of claim 11 , wherein the step of growing the first insulator liner and the second insulator liner comprises growing oxide in the first trench and the second trench.
16. The method of claim 11 , wherein:
the semiconductor layer has a top surface;
the second trench has a corner where the trench adjoins the top surface of the semiconductor layer; and
the step of growing the first insulator liner and the second insulator liner comprises rounding of the corner of the second trench.
17. The method of claim 16 , wherein the corner is semiconductor.
18. The method of claim 11 , wherein the step of etching comprises leaving at least 100 Angstroms of the first insulating liner.
19. The method of claim 11 , wherein the step of etching comprises removing the first insulating liner.
20. The method of claim 11 , further comprising forming a barrier layer and a stress relief layer over the semiconductor layer in areas adjacent to the first trench and the second trench.
21. The method of claim 20 , wherein the barrier layer comprises nitride and the stress relief layer comprises oxide.
22. A method for forming a semiconductor device structure in a semiconductor layer, comprising:
forming a first trench of a first width in the semiconductor layer;
forming a second trench of a second width greater than the first width in the second semiconductor layer;
growing a first insulator liner in the first trench and a second insulator liner in the second trench;
etching a portion of the first insulator liner; and
depositing an insulating layer in the first trench.
23. The method of claim 22 further comprising
forming a mask over the second trench prior to the step of etching; and
removing the mask prior to the step of depositing.
24. The method of claim 22 , wherein the step of etching further comprises etching a portion of the second insulator liner and leaves at least 50 Angstroms of the first insulator liner and 50 Angstroms of the second liner.
25. A method for forming a semiconductor device structure in a semiconductor layer, comprising:
forming a first trench of a first width in the semiconductor layer;
forming a second trench of a second width in the second semiconductor layer;
growing a first insulator liner in the first trench and a second insulator liner in the second trench;
etching a portion of the first insulator liner and a portion of the second insulator liner; and
depositing an insulating layer in the first trench and the second trench.
26. The method of claim 25 , wherein the step of etching comprises a wet etch.
27. The method of claim 26 , wherein the wet etch uses hydrofluoric acid.
28. The method of claim 25 , wherein the first insulator and the second insulator liner comprises thermal oxide.
29. The method of claim 25 , wherein the step of depositing comprises filling the first trench and second trench.
30. The method of claim 29 , wherein the insulating layer comprises high density plasma oxide.
31. A method for forming a semiconductor device structure in a semiconductor layer having a top surface, comprising:
forming a first trench of a first width in the semiconductor layer and having a first corner at the surface of the semiconductor layer;
forming a second trench of a second width greater than the first trench in the second semiconductor layer and having a second corner at the surface of the semiconductor layer;
growing a first insulator liner in the first trench and a second insulator liner in the second trench to achieve a radius of curvature of at least 200 Angstroms in the first and second corner;
etching a portion of the first insulator liner and a portion of the second insulator liner; and
depositing an insulating layer in the first trench and the second trench that fills the first and second trenches, wherein the insulating layer is free of voids.
32. The method of claim 31 , wherein the first insulator liner and the second insulator liner are thermal oxide.
33. The method of claim 31 , wherein the step of etching leaves the first insulator liner and the second insulator liner at a thickness sufficiently small to allow for completely filling the first trench with the insulating layer without voids in the insulating layer.
34. The method of claim 33 , wherein the insulating layer comprises high density plasma oxide.
35. The method of claim 31 , wherein the step of etching is further characterized as leaving at least 50 Angstroms of the first insulator liner and the second insulator liner.