Sensing of memory integrated circuits
View Patent ↗A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for asymmetry that exists between cells on bitline true and bitline complement. The first reference voltage is used for sensing a cell on bitline true while the second reference voltage is used for sensing a cell on bitline complement.
1. An integrated circuit comprising:
a first bitline with a plurality of memory cells;
a second bitline with a plurality of memory cells;
a sense amplifier having an inverting terminal coupled to the first bitline and a non-inverting terminal coupled to second bitline; and
a reference voltage selection circuit coupled to the sense amplifier, the reference selection circuit generating either a first reference voltage for reading one of the plurality of memory cells on the first bitline or a second reference voltage for reading one of the plurality of memory cells on the second bitline.
2. The integrated circuit of claim 1 wherein the memory cells are ferroelectric memory cells.
3. The integrated circuit of claim 1 wherein the reference voltage selection circuit comprises an output terminal coupled to the sense amplifier.
4. The integrated circuit of claim 1 , 2 or 3 wherein the reference voltage selection circuit generates either the first or second reference voltage at the output terminal for reading one of the plurality of memory cells on the first or second bitline.
5. The integrated circuit of claim 4 wherein the reference voltage selection circuit comprises a first reference generator for generating the first reference voltage and a second reference voltage generator for generating the second reference voltage.
6. The integrated circuit of claim 5 further comprises:
a first switch, the first switch selectively couples the first reference generator to the output of the reference voltage selection circuit; and
a second switch, the second switch selectively couples the second reference generator to the output of the reference voltage selection circuit.
7. The integrated circuit of claim 6 wherein the first and second switches are transistors.
8. The integrated circuit of claim 6 wherein the reference voltage selection circuit further comprises a select control circuit, the select control circuit receives input information and controls the first and second switches.
9. The integrated circuit of claim 8 wherein the input information comprises addressing information.
10. The integrated circuit of claim 8 wherein the input information comprises the least significant bit of the address.
11. The integrated circuit of claim 4 wherein the reference voltage selection circuit further comprises a select control circuit, the select control circuit receives input information and causes the reference selection circuit to generate the first or second reference voltage.
12. The integrated circuit of claim 11 wherein the input information comprises addressing information.
13. The integrated circuit of claim 11 wherein the input information comprises the least significant bit of the address.
14. The integrated circuit of claim 1 wherein the reference voltage selection circuit comprises a first reference generator for generating the first reference voltage and a second reference voltage generator for generating the second reference voltage.
15. The integrated circuit of claim 14 further comprises:
a first switch, the first switch selectively couples the first reference generator to the sense amplifier to provide the sense amplifier with the first reference voltage; and
a second switch, the second switch selectively couples the second reference generator to the sense amplifier to provide the sense amplifier with second reference voltage.
16. The integrated circuit of claim 15 wherein the first and second switches are transistors.
17. The integrated circuit of claim 16 wherein the reference voltage selection circuit further comprises a select control circuit, the select control circuit receives input information and controls the first and second switches.
18. The integrated circuit of claim 17 wherein the input information comprises addressing information.
19. The integrated circuit of claim 17 wherein the input information comprises the least significant bit of the address.
20. The integrated circuit of claim 14 wherein the reference voltage selection circuit further comprises a select control circuit, the select control circuit receives input information and causes the reference selection circuit to provide the first or second reference voltage.
21. The integrated circuit of claim 20 wherein the input information comprises addressing information.
22. The integrated circuit of claim 20 wherein the input information comprises the least significant bit of the address.