Two mask floating gate EEPROM and method of making
View Patent ↗There is provided a floating gate transistor, such as an EEPROM transistor, and method of making the transistor using two masking steps. The method of making a transistor includes patterning a floating gate layer using a first photoresist mask to form a floating gate rail and doping an active area using the floating gate rail as a mask to form source and drain regions in the active area. The method also includes patterning a control gate layer, a control gate dielectric layer, the floating gate rail, a tunnel dielectric layer and the active area using a second photoresist mask to form a control gate, a control gate dielectric, a floating gate, a tunnel dielectric and a channel island region.
1. An floating gate transistor, comprising:
a channel island region;
a source region located adjacent to a first side of the channel island region;
a drain region located adjacent to a second side of the channel island region;
a tunneling dielectric located above the channel island region;
a floating gate having a first, second, third and fourth side surfaces, wherein the floating gate is located above the tunneling dielectric;
a control gate dielectric located above the floating gate;
a control gate located above the control gate dielectric; and
wherein first and second side surfaces of the control gate are aligned to third and fourth side surfaces of the channel island region, and to the third and the fourth side surfaces of the floating gate.
2. The transistor of claim 1 , wherein the first and the second side surfaces of the control gate are aligned to side surfaces of the control gate dielectric and to side surfaces of the tunneling dielectric.
3. The transistor of claim 1 , wherein:
the control gate dielectric is located on a top surface of the floating gate and on upper portions of the first and the second side surfaces of the floating gate; and
the control gate is located on the control gate dielectric above a top surface of the floating gate and laterally adjacent to the upper portions of the first and the second side surfaces of the floating gate.
4. The transistor of claim 3 , wherein the control gate comprises a portion of a word line that extends in a direction substantially parallel to a source-channel-drain direction of the transistor.
5. The transistor of claim 4 , further comprising:
an intergate insulating layer located above the source and drain regions, laterally adjacent to lower portions of the first and the second side surfaces of the floating gate and below a bottom surface of the control gate;
a first bit line contacting the source region; and
a second bit line contacting the drain region.
6. The transistor of claim 5 , wherein the first and the second bit lines are located under the intergate insulating layer, and extend in a direction substantially perpendicular to the source-channel-drain direction.
7. The transistor of claim 6 , further comprising:
sidewall spacers located between the intergate insulating layer and the lower portions of the first and the second side surfaces of the floating gate; and
metal silicide regions contacting the bit lines.
8. The transistor of claim 7 , wherein the source and the drain regions comprise a heavily doped portion and a lightly doped portion.
9. The transistor of claim 1 , wherein the source and the drain regions are located asymmetrically with respect to the floating gate.
10. The transistor of claim 1 , wherein the transistor is formed using two photolithographic masking steps.
11. The transistor of claim 1 , wherein:
the source, the drain and the channel island region are formed in a polysilicon active layer, which is located above a substrate; and
the transistor comprises a TFT EEPROM.
12. A three dimensional nonvolatile memory array, comprising:
a plurality of vertically separated device levels, each level comprising an array of TFT EEPROMs of claim 11 ;
a plurality of bit line columns in each device level, each bit line contacting the source or the drain regions of the TFT EEPROMs;
a plurality of word line rows in each device level; and
at least one interlayer insulating layer located between the device levels.
13. The array of claim 12 , wherein:
the columns of bit lines extend substantially perpendicular to a source-channel-drain direction of the TFT EEPROMs;
each word line contains the control gates of the TFT EEPROMs, and the rows of word lines extend substantially parallel to the source-channel-drain direction of the TFT EEPROMs; and
the floating gates of the TFT EEPROMs comprise posts located between the control gates, the channel region islands and an intergate insulating layer.
14. The array of claim 13 , wherein the bit lines in each device level comprise rails which extend under the intergate insulating layer.
15. The array of claim 14 , wherein:
the rails comprise silicide layers over doped semiconductor regions;
the doped semiconductor regions comprise the TFT EEPROM source and drain regions in areas where the doped semiconductor regions are located adjacent to the TFT EEPROM channels; and
the array comprises a NVG, a DuSNOR or a SSL-NOR three dimensional array.
16. The array of claim 12 , further comprising an interlevel interconnect which connects devices on different device levels, wherein at least a portion of the word line row comprises the same layer as the interlevel interconnect.
17. The array of claim 12 , further comprising an insulating fill layer located between adjacent rail stacks, the rail stacks comprising the control gate, the control gate dielectric, the floating gate, the tunnel dielectric and the channel island region.