Sequential test pattern generation using clock-control design for testability structures
View Patent ↗Techniques for testing a sequential circuit comprising a plurality of flip-flops or other types of registers. The circuit is first configured such that substantially all feedback loops associated with the registers, other than one or more self-loops each associated with a corresponding one of the registers, are broken. Test patterns are then generated for application to the circuit. The test patterns are applied to the circuit in conjunction with partitioned clock signals each of which is associated with a corresponding level of the circuit containing at least one of the self-loops.
1. A method of performing test pattern generation for a circuit, the method comprising the steps of:
separating the circuit into a plurality of overlapping pipelines by controlling corresponding clocks for one or more registers of the circuit so as to break feedback loops of the circuit; and
processing each of the pipelines separately in order to determine if particular target faults are detectable in the pipelines.
2. The method of claim 1 wherein each of at least a subset of the registers of the circuit is controlled by an independent clock.
3. The method of claim 1 wherein a given one of the clocks associated with at least one of the registers is controlled so as to break a particular feedback loop of the circuit by freezing that clock.
4. The method of claim 1 wherein each of at least a subset of the overlapping pipelines comprises a balanced pipeline in which every path between two combinational blocks C i and C j of the circuit passes through the same number of registers.
5. The method of claim 1 wherein for a given one of the pipelines each of a plurality of flip-flops associated with a register having a clock which has been frozen in that pipeline is processed as a primary input of the circuit having a frozen value that cannot be changed during the test pattern generation process.
6. The method of claim 1 wherein for a given one of the pipelines combinational logic of the circuit that feeds only one or more registers having clocks which have been frozen in that pipeline is removed from that pipeline.
7. The method of claim 1 wherein for a given one of the pipelines any one of the registers having a clock which is not frozen and which feeds primary outputs of the circuit is designated as a transparent register in that pipeline.
8. The method of claim 1 wherein for a given one of the pipelines any one of the registers having a clock which is not frozen and which feeds only combinational logic of the circuit that feeds one or more registers having clocks which are frozen in the given pipeline is designated as a capture register and cannot be used to detect faults in the given pipeline.
9. The method of claim 1 wherein the processing step further comprises a first processing step which detects target faults in a single time frame, and a second processing step which detects target faults in two or more time frames.
10. The method of claim 9 wherein the first processing step generates as many combinational test vectors as possible for each of at least a subset of the pipelines.
11. The method of claim 9 wherein the second processing step generates a sequence of two or more combinational test vectors for a specified number of two or more time frames for each of at least a subset of the pipelines.
12. The method of claim 1 wherein at least the separating and processing steps are implemented in a test generator which is external to the circuit.
13. The method of claim 1 wherein at least the separating and processing steps are implemented in a test generator which is embedded within the circuit in a built-in self-test (BIST) configuration, the test generator generating one or more combinational vectors in a random manner.
14. An apparatus for performing test pattern generation for a circuit, the apparatus comprising:
a processor-based device operative to separate the circuit into a plurality of overlapping pipelines by controlling corresponding clocks for one or more registers of the circuit so as to break feedback loops of the circuit, and to process each of the pipelines separately in order to determine if particular target faults are detectable in the pipelines.
15. The apparatus of claim 14 wherein each of at least a subset of the registers of the circuit is controlled by an independent clock.
16. The apparatus of claim 14 wherein a given one of the clocks associated with at least one of the registers is controlled so as to break a particular feedback loop of the circuit by freezing that clock.
17. The apparatus of claim 14 wherein each of at least a subset of the overlapping pipelines comprises a balanced pipeline in which every path between two combinational blocks C i and C j of the circuit passes through the same number of registers.
18. The apparatus of claim 14 wherein for a given one of the pipelines each of a plurality of flip-flops associated with a register having a clock which has been frozen in that pipeline is processed as a primary input of the circuit having a frozen value that cannot be changed during the test pattern generation process.
19. The apparatus of claim 14 wherein for a given one of the pipelines combinational logic of the circuit that feeds only one or more registers having clocks which have been frozen in that pipeline is removed from that pipeline.
20. The apparatus of claim 14 wherein for a given one of the pipelines any one of the registers having a clock which is not frozen and which feeds primary outputs of the circuit is designated as a transparent register in that pipeline.
21. The apparatus of claim 14 wherein for a given one of the pipelines any one of the registers having a clock which is not frozen and which feeds only combinational logic of the circuit that feeds one or more registers having clocks which are frozen in the given pipeline is designated as a capture register and cannot be used to detect faults in the given pipeline.