Hermetic electric component package
View Patent ↗An electric component package having a base and a lid, the base and lid defining a hermetically sealed cavity therebetween for accommodating an electric component. The base includes at least one conductive via extending therethrough, allowing control and/or input/output (I/O) ports associated with the electric component to be coupled to the conducive vias to pass signals between the sealed cavity and the exterior of the package without passing through the junction between the base and lid. The electric component package can be produced at the wafer level using conventional silicon wafer integrated circuit manufacturing machinery prior to separating the wafer into a plurality of devices.
1. A process for fabricating an electric component package having a sealed cavity for accommodating an electric component, comprising the steps of:
etching a semiconductor base layer having first and second opposing surfaces to form at least one pedestal on said first surface;
applying a layer of dielectric material to said first surface of said etched semiconductor base layer;
grinding said dielectric layer to expose a surface of said at least one pedestal;
establishing an electric component on said ground dielectric layer, said electric component having at least one port coupled to said exposed surface of said at least one pedestal;
attaching a lid to said ground dielectric layer, said lid having a cavity for accommodating said electric component; and
grinding said semiconductor base layer on said second surface to expose said dielectric layer, said at least one pedestal forming a conductive via extending through said dielectric layer.
2. The method of claim 1 , wherein all steps are performed at wafer level.
3. The method of claim 1 , wherein said base and said lid have approximately equal coefficients of thermal expansion.
4. The method of claim 1 , wherein said component is hermetically sealed within said cavity between said base and said lid when said lid is attached to said base.
5. The process of claim 1 , further comprising:
depositing a base seal ring on said ground dielectric layer, said base seal ring surrounding a footprint of said electric component and said via.
6. The process of claim 1 , further comprising the step of fabricating said lid by etching a semiconductor lid layer.
7. The process of claim 6 , wherein said lid fabrication step comprises at least the steps of:
depositing a lid seal ring on a first surface of said semiconductor lid layer, said lid seal ring coupled to said base seal ring in said attaching step; and
etching said first surface of said semiconductor lid layer to form said cavity using said lid seal ring as an etch mask.
8. The process of claim 1 , further comprising the step of forming a solder bump on said second surface, said solder bump coupled to said at least one electrically isolated pedestal.
9. The process of claim 1 , said establishing step comprising at least the step of:
building said component on said ground dielectric layer.
10. The process of claim 1 , said establishing step comprising at least the step of:
placing said component on said ground dielectric layer.
11. The process of claim 10 , wherein said placing step comprises:
attaching said component to said ground dielectric layer; and
electrically coupling said at least one port to said exposed surface of said at least one pedestal.
12. The process of claim 11 , wherein said coupling step comprises at least the step of:
wirebonding said at least one port to said exposed surface of said at least one pedestal.
13. The process of claim 11 , wherein said coupling step comprises at least the step of:
attaching said at least one port to said exposed surface of said at least one pedestal with a solder ball.
14. The process of claim 1 , wherein said applying step comprises at least the step of:
fusing said layer of dielectric material to said first surface of said etched semiconductor base layer.
15. The process of claim 1 , further comprising the step of:
applying at least one layer of metal said first surface of said etched semiconductor base layer prior to applying said layer of dielectric material.