Bi-directional serializer/deserializer with discretionary loop-back
A serializer/deserializer pair with a discretionary loop-back mechanism is disclosed that enables a redundant high-bandwidth node architecture that benefits from the clever re-use of two identical integrated circuits. The first is an add/drop multiplexor and the second comprises the serializer/deserializer pair with discretionary loop-back. The illustrative embodiment comprises: a first serializer that serializes a first series of r-bit words to generate a first series of s-bit words; a first deserializer that deserializes a second series of s-bit words to generate a second series of r-bit words; and a multiplexor for selecting a third series of r-bit words from the first series of r-bit words and the second series of r-bit words; wherein r and s are both positive integers and r≧s.
1. An integrated circuit comprising:
a first serializer that serializes a first series of r-bit words to generate a first series of s-bit words;
a first deserializer that deserializes a second series of s-bit words to generate a second series of r-bit words; and
a multiplexor for selecting a third series of r-bit words from said first series of r-bit words and said second series of r-bit words;
wherein r and s are both positive integers and r≧s.
2. The integrated circuit of claim 1 wherein said first serializer adds parity bits to said first series of r-bit words to enable the forward error correction of said first series of s-bit words.
3. The integrated circuit of claim 1 wherein said first serializer adds framing bits to said first series of r-bit words to enable the frame synchronization of said first series of s-bit words.
4. The integrated circuit of claim 1 wherein said first deserializer performs forward error correction on said second series of s-bit words.
5. The integrated circuit of claim 1 further comprising:
a first plurality of drivers for driving said first series of s-bit words off of said integrated circuit via a first plurality of pads; and
a second plurality of drivers for driving said first series of s-bit words off of said integrated circuit via a second plurality of pads.
6. The integrated circuit of claim 1 wherein said first series of s-bit words and said third series of r-bit words are driven off of said integrated circuit; and
wherein said first series of r-bit words and said second series of s-bit words are received from off of said integrated circuit.
7. The integrated circuit of claim 1 further comprising a second deserializer that deserializes a third series of s-bit words to generate a fourth series of r-bit words; and
wherein said multiplexor selects said third series of r-bit words from said first series of r-bit words, said second series of r-bit words, and said fourth series of r-bit words.
8. The integrated circuit of claim 7 wherein said second deserializer performs forward error correction on said third series of s-bit words.
9. An integrated circuit comprising:
a first serializer that serializes a first series of r-bit words to generate a first series of s-bit words;
a first deserializer that deserializes said first series of s-bit words to generate a second series of r-bit words;
a second deserializer that deserializes a second series of s-bit words to generate a third series of r-bit words; and
a multiplexor for selecting a fourth series of r-bit words from said second series of r-bit words and said third series of r-bit words;
wherein r and s are both positive integers and r≧s.
10. The integrated circuit of claim 9 wherein said first serializer adds parity bits to said first series of r-bit words to enable the forward error correction of said first series of s-bit words.
11. The integrated circuit of claim 9 wherein said first serializer adds framing bits to said first series of r-bit words to enable the frame synchronization of said first series of s-bit words.
12. The integrated circuit of claim 9 wherein said first deserializer performs forward error correction on said second series of s-bit words.
13. The integrated circuit of claim 9 further comprising:
a first plurality of drivers for driving said first series of s-bit words off of said integrated circuit via a first plurality of pads; and
a second plurality of drivers for driving said first series of s-bit words off of said integrated circuit via a second plurality of pads.
14. The integrated circuit of claim 9 wherein said first series of s-bit words and said fourth series of r-bit words are driven off of said integrated circuit; and
wherein said first series of r-bit words and said second series of s-bit words are received from off of said integrated circuit.
15. The integrated circuit of claim 9 further comprising a third deserializer that deserializes a third series of s-bit words to generate a fifth series of r-bit words; and
wherein said multiplexor selects said fourth series of r-bit words from said second series of r-bit words, said third series of r-bit words, and said fifth series of r-bit words.
16. The integrated circuit of claim 15 wherein said third deserializer performs forward error correction on said third series of s-bit words.
17. An integrated circuit comprising:
a first serializer that serializes a first series of r-bit words to generate a first series of s-bit words;
a first multiplexor for selecting a second series of s-bit words from said first series of s-bit words and a third series of s-bit words; and
a first deserializer that deserializes said second series of s-bit words to generate a second series of r-bit words;
wherein r and s are both positive integers and r≧s.
18. The integrated circuit of claim 17 wherein said first serializer adds parity bits to said first series of r-bit words to enable the forward error correction of said first series of s-bit words.
19. The integrated circuit of claim 17 wherein said first serializer adds framing bits to said first series of r-bit words to enable the frame synchronization of said first series of s-bit words.
20. The integrated circuit of claim 17 wherein said first deserializer performs forward error correction on said second series of s-bit words.
21. The integrated circuit of claim 17 further comprising:
a first plurality of drivers for driving said first series of s-bit words off of said integrated circuit via a first plurality of pads; and
a second plurality of drivers for driving said first series of s-bit words off of said integrated circuit via a second plurality of pads.
22. The integrated circuit of claim 17 further comprising:
a second deserializer that deserializes a fourth series of s-bit words to generate a third series of r-bit words; and
a second multiplexor for selecting a fourth series of r-bit words from said second series of r-bit words and said third series of r-bit words.
23. The integrated circuit of claim 22 wherein said second deserializer performs forward error correction on said fourth series of s-bit words.
24. The integrated circuit of claim 22 wherein said first series of s-bit words and said fourth series of r-bit words are driven off of said integrated circuit; and
wherein said first series of r-bit words, said third series of s-bit words, and said fourth series of s-bit words are received from off of said integrated circuit.