Composite add/drop multiplexor with crisscross loop back
A composite add/drop multiplexor architecture is disclosed that facilitates the loop-back of a signal in a composite add/drop multiplexor (e.g., a SONET/SDH node, a dense wavelength division multiplexed node, etc.) that uses automatic protection switching.
1. An apparatus comprising:
(1) a first integrated circuit for transmitting a first series of r-bit words and a second series of r-bit words;
(2) a second integrated circuit for receiving a third series of r-bit words and a fourth series of r-bit words;
(3) a third integrated circuit comprising:
(a) a first serializer for serializing said first series of r-bit words to generate a first series of s-bit words,
(b) a first deserializer for deserializing a second series of s-bit words to generate a fifth series of r-bit words, and
(c) a first multiplexor for selecting said third series of r-bit words from said first series of r-bit words and said fifth series of r-bit words; and
(4) a fourth integrated circuit comprising:
(a) a second serializer for serializing said second series of r-bit words to generate a third series of s-bit words, and
(b) a second descrializer for deserializing a fourth series of s-bit words to generate a sixth series of r-bit words, and
(c) a second multiplexor for selecting said fourth series of r-bit words from said second series of r-bit words and said sixth series of r-bit words;
wherein r and s are both positive integers and r>s.
2. The apparatus of claim 1 wherein:
(3) said third integrated circuit further comprises:
(d) a first plurality of drivers for driving said first series of s-bit words off of said third integrated circuit via a first plurality of pads, and
(e) a second plurality of drivers for driving said first series of s-bit words off of said third integrated circuit via a second plurality of pads; and
(4) said fourth integrated circuit further comprises:
(d) a third plurality of drivers for driving said third series of s-bit words off of said fourth integrated circuit via a third plurality of pads, and
(e) a fourth plurality of drivers for driving said third series of s-bit words off of said fourth integrated circuit via a fourth plurality of pads.
3. The apparatus of claim 1 wherein:
(3) said third integrated circuit further comprises:
(e) a third deserializer for deserializing a fifth series of s-bit words to generate a seventh series of r-bit words, and
wherein said first multiplexor selects said third series of r-bit words from said first series of r-bit words, said fifth series of r-bit words, and said seventh series of r-bit words; and
(4) said fourth integrated circuit further comprises:
(e) a fourth deserializer for deserializing a sixth series of s-bit words to generate an eighth series of r-bit words, and
wherein said second multiplexor selects said fourth series of r-bit words from said second series of r-bit words, said sixth series of s-bit words, and said eighth series of r-bit words.
4. The apparatus of claim 1 wherein said first series of s-bit words is driven off of said third integrated circuit, and wherein said third series of s-bit words is driven off of said fourth integrated circuit.
5. An apparatus comprising:
(1) a first integrated circuit for transmitting a first series of r-bit words and a second series of r-bit words;
(2) a second integrated circuit for receiving a third series of r-bit words and a fourth series of r-bit words;
(3) a third integrated circuit comprising:
(a) a first serializer for serializing said first series of r-bit words to generate a first series of s-bit words,
(b) a first deserializer for deserializing said first series of s-bit words to generate a fifth series of r-bit words,
(c) a second deserializer for deserializing a second series of s-bit words to generate a sixth series of r-bit words, and
(d) a first multiplexor for selecting said third series of r-bit words from said fifth series of r-bit words and said sixth series of r-bit words; and
(4) a fourth integrated circuit comprising:
(a) a second serializer for serializing said second series of r-bit words to generate a third series of s-bit words,
(b) a third deserializer for deserializing said third series of s-bit words to generate a seventh series of r-bit words,
(c) a fourth deserializer for deserializing a fourth series of s-bit words to generate an eighth series of r-bit words, and
(d) a second multiplexor for selecting said fourth series of r-bit words from said seventh series of r-bit words and said eighth series of r-bit words.
6. The apparatus of claim 5 wherein:
(3) said third integrated circuit further comprises:
(e) a first plurality of drivers for driving said first series of s-bit words of said third integrated circuit via a first plurality of pads, and
(f) a second plurality of drivers for driving said first series of s-bit words off of said third integrated circuit via a second plurality of pads; and
(4) said fourth integrated circuit further comprises:
(e) a third plurality of drivers for driving said third series of s-bit words off of said fourth integrated circuit via a third plurality of pads, and
(f) a fourth plurality of drivers for driving said third series of s-bit words off of said fourth integrated circuit via a fourth plurality of pads.
7. The apparatus of claim 5 wherein:
(3) said third integrated circuit further comprises:
(e) a fifth deserializer for deserializing a fifth series of s-bit words to generate a ninth series of r-bit words, and
wherein said first multiplexer selects said third series of r-bit words from said fifth series of r-bit words, said sixth series of r-bit words, and said ninth series of r-bit words; and
(4) said fourth integrated circuit further comprises:
(e) a sixth deserializer for deserializing a sixth series of s-bit words to generate a tenth series of r-bit words, and
wherein said second multiplexor selects said fourth series of r-bit words from said seventh series of r-bit words, said eight series of r-bit words, and said tenth series of r-bit words.
8. The apparatus of claim 5 wherein said first series of s-bit words is driven off of said third integrated circuit, and wherein said third series of s-bit words is driven off of said fourth integrated circuit.
9. An apparatus comprising:
(1) a first integrated circuit for transmitting a first series of r-bit words and a second series of r-bit words;
(2) a second integrated circuit for receiving a third series of r-bit words and a fourth series of r-bit words;
(3) a third integrated circuit comprising:
(a) a first serializer for serializing said first series of r-bit words to generate a first series of s-bit words,
(h) a first multiplenor for selecting a third series of s-bit words from a second series of s-bit words and said first series of s-bit words, and
(c) a first deserializer for deserializing said third series of s-bit words;
(4) a fourth integrated circuit comprising:
(a) a second scrializer for scrializing said second series of r-bit words to generate a fourth series of s-bit words,
(b) a second multiplexor for selecting a sixth series of s-bit words from a fifth series of s-bit words and said fourth series of s-bit words, and
(c) a second deserializer for deserializing said sixth series of s-bit words.
10. The apparatus of claim 9 wherein:
(3)(a) said first deseriaiizer generates said third series of r-bit words by deserializing said third series of s-bit words, and
(4)(a) said second deserializer generates said fourth series of r-bit words by deserializing said sixth series of s-bit words.
11. The apparatus of claim 9 wherein:
(3) said third integrated circuit further comprises:
(d) a first plurality of drivers for driving said first series of s-bit words off of said third integrated circuit via a first plurality of pads, and
(e) a second plurality of drivers for driving said first series of s-bit words off of said third integrated circuit via a second plurality of pads; and
(4) said fourth integrated circuit further comprises:
(d) a third plurality of drivers for driving said fourth series of s-bit words off of said fourth integrated circuit via a third plurality of pads, and
(e) a fourth plurality of drivers for driving said fourth series of s-bit words off of said fourth integrated circuit via a fourth plurality of pads.
12. An apparatus comprising:
(1) a first integrated circuit for transmitting a first series of r-bit words and a second series of r-bit words;
(2) a second integrated circuit for receiving a third series of r-bit words and a fourth series of r-bit words;
(3) a third integrated circuit comprising:
(a) a first serializer for serializing said first series of r-bit words to generate a first series of s-bit words,
(b) a first multiplexor for selecting a third series of s-bit words from said first series of s-bit words and a fourth series of s-bit words,
(c) a first deserializer for deserializing said third series of s-bit words to generate a fifth series of r-bit words,
(d) a second deserializer for deserializing a fifth series of s-bit words to generate a sixth series of r-bit words, and
(e) a second multiplexor for selecting said third series of r-bit words from said fifth series of bit words and said sixth series of r-bit words;
(4) a fourth integrated circuit comprising:
(a) a second serializer for serializing said second series of r-bit words to generate a second series of s-bit words,
(b) a third multiplexor for selecting a sixth series of s-bit words from said second series of s-bit words and a seventh series of s-bit words,
(c) a third deserializer for deserializing said sixth series of s-bit words to generate a seventh series of r-bit words,
(d) a fourth deserializer for deserializing an eighth series of s-bit words to generate an eighth series of r-bit words, and
(e) a fourth multiplexor for selecting said fourth series of ibit words from said seventh series of r-bit words and said eighth series of r-bit words.
13. The apparatus of claim 12 wherein said first series of s-bit words is driven off of said third integrated circuit, and wherein said third series of s-bit words is driven off of said fourth integrated circuit.