Single-instruction multiple-data (SIMD)-based algorithms for processing video data
View Patent ↗In a video encoder/decoder, a method processes a discrete cosine transform (DCT) block of coefficients. The method receives a DCT block of coefficients, and linearizes the DCT block of coefficients into a one dimensional array of sequentially arranged coefficients. The method stores a portion of the one dimensional array of coefficients in a register, the portion including at least two sequentially arranged coefficients. The stored portion of coefficients in the register is processed. A next portion of coefficients in the one dimensional array is processed. This is repeated until the entire DCT block of coefficients have been loaded into the register. The processing may include computing a run length value, finding a class number, or determining dequantized coefficients of a DCT block.
1. A method of processing a discrete cosine transform (DCT) block of coefficients, the method comprising the steps of:
(a) receiving a DCT block of coefficients;
(b) linearizing the DCT block of coefficients into a one dimensional array of sequentially arranged DCT coefficients;
(c) concurrently storing a portion of the one dimensional array of DCT coefficients in a first register, the portion including at least two sequentially arranged DCT coefficients;
(d) concurrently processing the stored portion of DCT coefficients in the first register, the processing including comparing the stored portion of DCT coefficients in the first register with values stored in a second register;
(e) indexing a run length table using a hash key obtained by a comparison in step (d) of the DCT coefficients in the first register with values stored in the second register;
(f) repeating steps (c) to (e) on a next portion of DCT coefficients in the one dimensional array to complete processing the DCT block of coefficients; and
(g) providing a result of the processing to a video encoder/decoder.
2. The method of claim 1 in which step (d) includes determining a number of sequentially arranged DCT coefficients having a zero value stored in the first register.
3. The method of claim 2 in which
step (d) includes simultaneously comparing the DCT coefficients stored in the first register with a set of zero values stored in the second register.
4. The method of claim 2 in which
step (d) includes simultaneously comparing the DCT coefficients stored in the first register with a set of zero values stored in a second register, and storing a result of the comparison;
step (e) includes applying a masking operation to the result of the comparison to obtain the hash key, and storing the hash key in a third register, and indexing the run length table using the hash key to determine a number of sequentially arranged DCT coefficients having zero values stored in the first register.
5. The method of claim 4 in which step (d) includes processing the stored portion of the DCT coefficients using streaming single-instruction-multiple-data extension 2 (SSE2) instructions for an Intel Pentium 4 processor.
6. The method of claim 1 in which
step (a) includes receiving a DCT block of 64 coefficients; and
step (c) includes storing 8 DCT coefficients in the first register.
7. A method of obtaining a run length value of a DCT block of coefficients in a video encoder/decoder, the method comprising the steps of:
(a) receiving a DCT block or coefficients;
(b) linearizing the DCT block of coefficients into a one dimensional array of sequentially arranged DCT coefficients;
(c) storing a portion of the one dimensional array of DCT coefficients in a register, the portion including at least two sequentially arranged DCT coefficients;
(d) concurrently comparing the DCT coefficients stored in the register with a set of zero values stored in another register; and
(e) determining a run length value of the DCT coefficients by indexing a run-length table using a hash key obtained responsive to the comparison of step (d).
8. The method of claim 7 further including the steps of:
(f) repeating steps (c) through (e) on a next portion of DCT coefficients in the one dimensional array; and
(g) updating the run length value after completing step (f).
9. The method of claim 7 in which
step (d) includes applying a mask function to the results of the comparison to obtain the hash key.
10. The method of claim 7 in which
step (a) includes receiving a DCT block of 64 coefficients; and
step (c) includes storing 8 DCT coefficients in the first register.
11. The method of claim 10 in which the register is a 128 bit register; and
step (c) includes storing 8 sequentially arranged DCT coefficients, each DCT coefficient having a 16 bit value.
12. The method of claim 7 in which step (d) prior to the comparison step includes the steps of determining whether the DCT coefficients stored in the register include a −1 value; determining whether the DCT coefficients stored in the register include a =1 value; and replacing each of the determined −1 value and the determined =1 value with a corresponding zero value.