Granted Patent B1

US 6,979,640 · App. 10/112,572 · Granted Dec 27, 2005

Abstract

Claims (51)

1. A method of making a semiconductor structure, comprising:

forming a hole through a first dielectric layer; followed by

extending the hole through an etch-stop layer, to expose a first conducting layer;

wherein the thickness of the etch-stop layer in the smallest dimension is at least one-half the smallest line width of the first conducting layer.

2. The method of claim 1 , further comprising:

filling the hole with a conductive material, to form a via; and

forming a second conducting layer, on the dielectric layer;

wherein the via electrically connects the first and second conducting layers.

3. The method of claim 2 , further comprising:

forming a second dielectric layer, on the second conductive layer; and

forming a third conducting layer, on the second dielectric layer.

4. The method of claim 2 , further comprising:

forming a capping layer, on the dielectric layer; and

lining the hole with a liner, prior to the filling of the hole;

wherein the capping layer is between the dielectric layer and the second conducting layer.

5. The method of claim 1 , wherein the first conducting layer is a local interconnect layer.

6. The method of claim 2 , wherein the first conducting layer comprises titanium,

the second conducting layer comprises at least one member selected from aluminum and copper,

the conductive material comprises at least one member selected from tungsten and aluminum,

the first dielectric layer comprises oxide, and

the etch-stop layer comprises nitride or oxynitride.

7. The method of claim 1 , wherein the thickness of the etch-stop layer in the smallest dimension is about one Lynch value.

8. A method of making a semiconductor structure, comprising:

forming an etch-stop layer on a first conducting layer; and

forming a first dielectric layer on the etch-stop layer;

wherein the forming of the dielectric layer is carried out before patterning the etch-stop layer, and

the thickness of the etch-stop layer in the smallest dimension is at least one-half the smallest line width of the first conducting layer.

9. The method of claim 8 , wherein the first conducting layer does not comprise a doped semiconductor.

10. The method of claim 9 , further comprising:

forming a hole through the first dielectric layer and the etch-stop layer;

filling the hole with a conductive material, to form a via; and

forming a second conducting layer on the first dielectric layer;

wherein the via electrically connects the first and second conducting layers.

11. The method of claim 10 , further comprising:

forming a second dielectric layer, on the second conducting layer; and

forming a third conducting layer, on the second dielectric layer.

12. The method of claim 10 , further comprising:

forming a capping layer, on the dielectric layer; and

lining the hole with a liner, prior to the filling of the hole;

wherein the capping layer is between the dielectric layer and the second conducting layer.

13. The method of claim 9 , wherein the first conducting layer is a local interconnect layer.

14. The method of claim 13 , wherein the first conducting layer comprises titanium,

the second conducting layer comprises at least one member selected from aluminum and copper, and

the conductive material comprises at least one member selected from tungsten and aluminum.

15. The method of claim 9 , wherein the thickness of the etch-stop layer in the smallest dimension is about one Lynch value.

16. A method of making a semiconductor device, comprising:

making a semiconductor structure by the method of claim 1 ; and

forming a semiconductor device from the semiconductor structure.

17. A method of making an electronic device, comprising:

making a semiconductor device by the method of claim 16 ; and

forming an electronic device comprising the semiconductor device.

Assignments (8)