Implementation of wait-states
View Patent ↗An improved implementation of wait-states in an SOC architecture with optimized performance is described. The clock input signal to the processor is modified during wait-states so that the wait signal does not have to be provided within a short setup time. Data integrity is maintained by providing alternative data paths during wait-states.
1. A method of implementing wait-states in an integrated circuit, comprising:
triggering the wait-states;
modifying a clock signal during the wait-states; and
applying the modified clock signal to a clock input port of a processor, the clock signal synchronizing data transfer between the processor and a unit.
2. A method of claim 1 wherein said unit comprises a memory module or a peripheral unit.
3. A method of claim 2 wherein the step of triggering the wait-states comprises asserting a wait signal.
4. A method of claim 2 wherein the step of modifying the clock signal comprises stopping the clock signal.
5. A method of claim 4 wherein the step of triggering the wait-states comprises asserting a wait signal.
6. A method of claim 1 wherein the step of modifying the clock signal comprises stopping the clock signal.
7. A method of claim 5 further including the step of applying the modified clock signal to a clock input port of the said unit.
8. A method of claim 6 wherein the step of triggering the wait-states comprises asserting a wait signal.
9. A method of claim 1 wherein the step of triggering the wait-states comprises asserting a wait signal.
10. A method of implementing wait-states in an integrated circuit, comprising:
triggering the wait-states;
modifying a clock signal during the wait-states;
applying the modified clock signal to a clock input port of a processor, the clock signal synchronizing data transfer between the processor and a unit; and
providing alternative data paths for maintaining data integrity.
11. A method of claim 8 wherein said unit comprises a memory module or a peripheral unit.
12. A method of claim 9 wherein the step of modifying the clock signal comprises stopping the clock signal.
13. A method of claim 11 wherein the step of triggering the wait-states comprises asserting a wait signal.
14. A methof of claim 13 wherein the step of modifying the clock signal comprises stopping the clock signal.
15. A method of claim 10 wherein the step of triggering the wait-states comprises asserting a wait signal.
16. A method of claim 13 wherein the step of modifying the clock signal comprises stopping the clock signal.
17. A method of claim 14 further including the step of applying the modified clock signal to a clock input port of the said unit.
18. A method of claim 8 wherein the step of providing alternative data paths comprises storing a current address and channeling the stored address to the address bus to maintain data integrity during the wait-states.
19. A method of claim 16 wherein said unit comprises a memory module or a peripheral unit.
20. A method of claim 18 wherein the step of triggering the wait-states comprises asserting a wait signal.
21. A method of claim 18 wherein the step of modifying the clock signal comprises stopping the clock signal.
22. A method of claim 21 wherein the step of triggering the wait-states comprises asserting a wait signal.
23. A method of claim 17 wherein the step of triggering the wait-states comprises asserting a wait signal.
24. A method of claim 19 wherein the step of modifying the clock signal comprises stopping the clock signal.
25. A method of claim 18 wherein the step of modifying the clock signal comprises stopping the clock signal.
26. A method of claim 19 further including the step of applying the modified clock signal to a clock input port of the said unit.
27. A method of claim 10 wherein the step of modifying the clock signal comprises stopping the clock signal.
28. A method of implementing wait-states in an integrated circuit, comprising:
triggering the wait-states by asserting a wait signal;
modifying a clock signal during the wait-states;
applying the modified clock signal to a clock input port of a processor, the clock signal synchronizing data transfer between the processor and a unit; and
providing alternative data paths for maintaining data integrity.