Granted Patent
Utility
US 6,549,445
· Confirmation No. 7519
SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF GLOBAL DATA LINES IN PARALLEL ARRANGEMENT WITH LOW PARASITIC CAPACITANCE, AND FABRICATION METHOD THEREOF
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2002-04-09 | TRNA |
Transmittal of New Application | 3 | View | |
| 2002-04-09 | SPEC |
Specification | 32 | View | |
| 2002-04-09 | CLM |
Claims | 6 | View | |
| 2002-04-09 | ABST |
Abstract | 1 | View | |
| 2002-04-09 | DRW |
Drawings-only black and white line drawings | 16 | View | |
| 2002-04-09 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Tsukasa Ooishi
Hyogo, JAPAN
Hiroaki Tanizaki
Hyogo, JAPAN
Attorneys & Agents of Record
Classification
USPC
365/63
G11C29/848
H10B12/50
H10B12/09
G11C7/18
Prosecution
- Examiner
- LE, THONG QUOC
- Art Unit
- 2818
- Docket No.
- 57454-494
- Confirmation No.
- 7519
Foreign Priority
2000-167643 (P)
·
2000-06-05
·
JAPAN
Publication
- Pub. No.
- US20020110016A1
- Pub. Date
- 2002-08-15
Patent Term Adjustment
0days
CHANGE OF ADDRESS
Recorded 2017-11-29
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2017-08-24
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2011-03-18
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Quick Facts
- Patent No.
- US 6,549,445
- App. No.
- 10/118,126
- Filed
- 2002-04-09
- Granted
- 2003-04-15
- Pub. No.
- US20020110016A1
- Examiner
- LE, THONG QUOC
- Art Unit
- 2818
- PTA
- 0 days
External Links