IP Library › Granted Patent US 6,852,607
Granted Patent B2
US 6,852,607 · App. 10/144,539 · Granted Feb 8, 2005

Wafer level package having a side package

Assignee: Samsung Electronics., LTD
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Quick Facts
Patent No.
US 6,852,607
App. No.
10/144,539
Granted
Feb 8, 2005
Kind
B2
Abstract

A method of manufacturing a wafer level package includes forming a semiconductor wafer including semiconductor chips, and forming a package body on the sides of each semiconductor chip. The package body is formed by forming a space between each semiconductor chip and potting a package material in the space, which can be a mold resin. The wafer is then separated into separate semiconductor chips by cutting through the package body.

Claims (28)

1. A method of manufacturing a wafer level package comprising:

forming a semiconductor wafer, wherein the semiconductor wafer includes a plurality of semiconductor chips, wherein each semiconductor chip of the plurality of semiconductor chips includes a plurality of electrode pads;

creating a gap between each said semiconductor chip of the plurality of semiconductor chips such that each said semiconductor chip is separate from each other;

providing a package material only to each said gap to form a package body on vertical sides of each semiconductor chip of the plurality of semiconductor chips.

2. The method of claim 1 , wherein forming the wafer further comprises:

forming a first insulating layer on the semiconductor wafer; and

exposing the plurality of electrode pads.

3. The method of claim 2 , wherein forming the first insulating layer on the semiconductor wafer comprises:

forming a passivation layer on the semiconductor wafer; and

forming the first insulating layer on the passivation layer.

4. The method of claim 2 , wherein forming the wafer further comprises:

forming a metal wiring layer on the first insulating layer, wherein the metal wiring layer is electrically connected to the electrode pads.

5. The method of claim 4 , wherein forming the wafer further comprises:

forming a second insulating layer on the metal wiring layer; and

providing openings in the metal wiring layer.

6. The method of claim 5 , wherein forming the wafer further comprises:

forming an electrical connection on the metal wiring layer through the opening.

7. The method of claim 1 , wherein the package material is a molded resin.

8. The method of claim 2 , further comprising: separating the wafer into a plurality of separate semiconductor chips.

9. The method of claim 8 , wherein separating the wafer comprises:

cutting the package body.

10. The method of claim 9 , wherein cutting the package body comprises:

cutting the package body with a rotating cutting blade.

11. The method of claim 1 , further comprising attaching a tape to a bottom surface of each said semiconductor chip.

12. The method of claim 11 , wherein the tape is an expandable tape.

13. The method of claim 1 , wherein the wafer level package includes

a semiconductor chip from the plurality of semiconductor chips, wherein the plurality of electrode pads are positioned on an active surface of the semiconductor chip; and

the package body formed on the sides of the semiconductor chip.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2002
From: SONG, YOUNG HEE; SON, MIN YOUNG; HA, WOONG KY
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 012905/0974 →
Priority Claims (1)
KR 2001-30372 · May 31, 2001 · national
Continuity (1)
Related Publication 20020180017A1 · Dec 5, 2002