Method for parallel simulation on a single microprocessor using meta-models
View Patent ↗The present invention generally relates to hardware development and design, and in particular it relates to a method for simulating hardware. A meta model ( 22 ) is compiled for integrating a plurality of n different instantiations ( 12 A, . . . 12 N) of the same hardware model, and facilities and signals of different instantiations are resolved by instantiation-specific name space specifications in a code switch ( 24,26 ). Thus, computing time is saved because by simulating the meta model, the processor resources, for instance, storage spaces, are utilized more efficiently.
1. A method for simulating a hardware logic circuit using a hardware model and a simulation environment test bench in which stimuli of the simulation are built-up and simulation result data is managed, the method comprising the steps of:
using a meta model compiled for integrating a plurality of n different instantiations of copies of the same hardware model for simulating multiple instances of the complete design with multiple instances of the test bench, which instantiations are identical but differ in a plurality of input variables,
resolving facilities and signals of different instantiations by instantiation-specific name space specifications,
running within one single simulation run on a single microprocessor system, said plurality of n different instantiations of the same hardware model,
associating each of a plurality of n input channels from environment codes with a respective one of model instantiations for stimuli input purposes with a dedicated code switch, and
associating each of a plurality of n output channels from said model instantiations with an invocation of a respective one of said environment codes with a respective code switch.
2. The method according to claim 1 comprising the steps of:
generating a test object for communicating with the meta model, and
generating a main program calling a plurality of n different instantiations of identical simulation models.
3. The method according to claim 1 in which said model-specific name space specifications is done by prefix or suffix name extensions of respective variables.
4. The method according to claim 1 further comprising the steps of:
monitoring events issued by the execution of model execution, and
invoking a respective environment code responsive to such event.
5. A method for compiling a meta model of a hardware design source comprising the steps of:
providing a facility for entering multiple instantiations of the same hardware simulation model for simulating multiple instances of the complete design with multiple instances of a test bench, which instantiations are copies of the hardware simulation model but differ in a plurality of input variables, with instantiation-specific name space specifications,
compiling said multiple instantiations into a single executable or object file of one single meta model,
running said single executable or object file within one single simulation run on a single microprocessor system, said multiple instantiations of said hardware simulation model,
associating each of a plurality of n input channels from environment codes with a respective one of said instantiations for stimuli input purposes with a dedicated code switch, and
associating each of a plurality of n output channels from said model instantiations with an invocation of a respective one of said environment codes with a respective code switch.