Communication system and methodology for addressing and sending data of dissimilar type and size across channels formed within a locally synchronized bus
View Patent ↗A communication system, network interface and communication port is provided that includes a media local bus. The local bus is connected between a controller and one or more multimedia devices located within a node of the communication system. The controller periodically broadcasts addressing signals to the source devices to synchronize data transmission from those devices according to those addresses. Source devices will thereafter transmit a command which signifies the type of data being transmitted from that source device within the address channel. The channel is maintained and data is transmitted until the next address is sent from the controller. Each channel can be set up in a customized fashion to add flexibility in channel length and data types being transferred throughout the local bus without having to assign fixed and regimented time slots for those data types and for each device connected to the local bus.
1. A port, comprising a plurality of addresses sent or received by the port, each of which specifics a unique channel comprising a source and a destination for a data transfer, wherein the number of bytes between a pair of addresses specifies a data transfer byte length for a channel addressed with an address prior to the pair of addresses.
2. The port as recited in claim 1 , wherein the address prior to the pair of addresses specifics the source and destination for the data transfer.
3. The port as recited in claim 1 , wherein the address prior to the pair of addresses is at least two bytes prior to the first address of the pair of addresses.
4. The port as recited in claim 1 , wherein the number of bytes between the pair of addresses is at least two bytes.
5. The port as recited in claim 1 , wherein each of the plurality of addresses comprises a byte having a logic low voltage value in a most significant bit location of the byte.
6. The port as recited in claim 1 , wherein the port is on a monolithic substrate.
7. The port as recited in claim 1 , wherein the port is embodied on a network interface configured between a bus and a network.
8. The port as recited in claim 1 , wherein the port is embodied upon a multimedia device.
9. A communication system, comprising:
a network interface, comprising:
a signal pin adapted to send a first address, followed by a second address, and followed by a third address;
a multimedia device, comprising:
a data pin adapted to send data from a source to a destination designated by the first address for a time duration between when the signal pin sends the second address and the third address.
10. The communication system as recited in claim 9 , wherein the network interface further comprises a clock pin adapted to send a clock, and wherein the first, second and third addresses as well as the data from the source to the destination are synchronized to the clock.
11. The communication system as recited in claim 9 , wherein the multimedia device further comprises a signal pin in communication with the signal pin of the network interface for sending a command between the second address and the third address to specify the type of data sent in accordance with the first address.
12. A network interfaced, comprising:
a clock pin;
a signal pin adapted to send a first address, followed by a second address, and followed by a third address; and
a data pin adapted to send data from a source to a destination designated by the first address for a time duration between when the signal pin sends the second address and the third address.
13. The network interface as recited in claim 12 , wherein the time duration occurs after the second address ends and before the third address begins.
14. The network interface as recited in claim 12 , wherein the clock pin is adapted to send a clock, and wherein the first address, second address, third address and data are synchronized to the clock.
15. The network interface as recited in claim 14 , wherein the time duration begins at a cycle of the clock immediately after the second address ends and the time duration ends at a cycle of the clock immediately before the third address begins.
16. The network interface as recited in claim 12 , wherein the signal pin is further adapted to send a command between the first address and the second address for specifying the type of data designated by the first address.
17. The network interface as recited in claim 12 , wherein the signal pin is further adapted to send a command between the second address and the third address for specifying the type of data designated by the first address.
18. The network interface as recited in claim 12 , wherein the signal pin is further adapted to send a command specifying the type of data designated by the first address.
19. The network interface as recited in claim 18 , wherein the type of data consists of packets of data sent from a multimedia player at a transfer rate dissimilar to the transfer rate of the data.
20. The network interface as recited in claim 18 , wherein the type of data consists of data streaming from the network onto the network interface at a transfer rate equal to the a transfer rate of the data.
21. The network interface as recited in claim 18 , wherein the type of data consists of data streaming from a multimedia player at a transfer rate equal to the transfer rate or the data.
22. The network interface as recited in claim 18 , wherein the type of data consists of packets of data sent from the network onto the network interface at a transfer rate dissimilar from to the a transfer rate of the data.
23. The network interface as recited in claim 12 , wherein the first, second and third addresses are each one byte in length with a logic low voltage value at the most significant bit location.
24. The network interface as recited in claim 12 , wherein the data sent from the data pin comprising at least a portion of a frame that is synchronized with a sync byte at the beginning of the frame comprising eight logic high voltage values.
25. A method for transmitting information, comprising:
transmitting a first address;
transmitting a second address;
transmitting data from a source to a destination specified by the first address; and
transmitting a third address thereupon terminating transmission of the data.