IP Library Granted Patent US 6,874,048
Granted Patent B2
US 6,874,048 · App. 10/157,673 · Granted Mar 29, 2005

Communication system and methodology for sending a designator for at least one of a set of time-division multiplexed channels forwarded across a locally synchronized bus

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Quick Facts
Patent No.
US 6,874,048
App. No.
10/157,673
Granted
Mar 29, 2005
Kind
B2
Abstract

A communication system, network interface and communication port is provided that includes a media local bus. The local bus is connected between a controller and one or more multimedia devices located within a node of the communication system. The controller periodically broadcasts sync signals to the source device, or devices, to synchronize data transmission partitioned into time slots. Each time slot represents is dedicated to a particular data type. Thus, time slot 1 can accommodate packetized data, time slot 2 can accommodate synchronous data, time slot 3 can accommodate control data, and time slot 4 can accommodate isochronous data. Various combinations and variations of those time slots can occur where fewer than four data types can be present within a frame or all four data types can be present. The local bus includes a signal line and one or more data lines.

Claims (46)

1. A port, comprising:

a data pin adapted to receive a frame comprising a first set of bytes time-division multiplexed with a second set of bytes, wherein the first set of bytes comprise packet data; and

a signal pin adapted to receive a sync signal followed by a command signal, wherein the sync signal indicates a boundary of said frame and said command signal occurs at approximately the same time as the first set of bytes for indicating a start of the packet data.

2. The port as recited in claim 1 , wherein the first set of bytes occur within the frame before the second set of bytes.

3. The port as recited in claim 1 , wherein the first set of bytes occur within the frame after the second set of bytes.

4. The port as recited in claim 1 , wherein the command signal occurs at approximately the same time as a first byte within the first set of bytes.

5. The port as recited in claim 1 , wherein the command signal comprises a code of eight bits with a logic low voltage value in the most significant bit location.

6. The port as recited in claim 1 , wherein the sync signal comprises a code of hexadecimal FF.

7. The port as recited in claim 1 , further comprising a plurality of devices connected by the bus in a ring or bus topology.

8. The port as recited in claim 1 , wherein the signal pin and the data pin are embodied on a monolithic substrate.

9. The port as recited in claim 1 , wherein the signal pin and the data pin are embodied on a network interface configured between a bus and a network.

10. The port as recited in claim 1 , wherein the signal pin and the data pin are embodied upon a multimedia device configured to receive the first set of bytes.

11. The port as recited in claim 1 , further comprising N data pins, where the sync signal comprises a pulse synchronized by a clock signal, wherein the sync signal is sent across the signal pin contemporaneous with M coded bits sent across the N data pins to signal the start of a frame of data.

12. The port as recited in claim 11 , wherein M equals eight.

13. The port as recited in claim 1 , further comprising N data pins, where the command signal comprises a pulse synchronized by a clock signal, wherein the command signal is sent across the signal pin contemporaneous with M coded bits sent across the N data pins to signal the start of a packet of data.

14. The port as recited in claim 13 , wherein M equals eight.

15. A communication system, comprising:

a network interface, comprising:

a data pin configured to send a frame of data partitioned according to timeslots;

a signal pin coupled to a generator for sending a sync code followed by a command code;

a multimedia device, comprising:

a data pin configured to receive the frame of data; and

a signal pin coupled to a decoder for receiving the sync code and the command code and for decoding the sync code to signify the beginning of the frame and for decoding the command code to signify the beginning of a data type within one of the data partitions.

16. The communication system as recited in claim 15 , wherein the data type within one of the data partitions is packetized data.

17. The communication system as recited in claim 15 , wherein the data type within another one of the data partitions is streaming data.

18. The communication system as recited in claim 15 , wherein the data pin on the network interface and the data pin on the multi-media device are connected by a conductor across which bi-directional communication occurs.

19. The communication system as recited in claim 15 , wherein the data pin on the network interface and the data pin on the multi-media device are connected by a conductor across on which uni-directional communication occurs.

20. The communication system as recited in claim 15 , wherein the sync code comprises a byte of hexadecimal FF, and wherein the command code comprises a byte having a logic low voltage value at the most significant bit location.

21. The communication system as recited in claim 15 , wherein the sync code comprises a byte length of logic high voltage values followed, exclusive of the sync code by a logic low voltage value.

22. A network interface, comprising:

a signal pin adapted for sending a sync signal followed by a command signal; and

at least one data pin adapted for sending at least one byte of a first series of bytes of data across a first channel followed by at least one byte of a second series of bytes of data across a second channel, wherein the first and second channels occur in time-divisional multiplexed sequence after the sync signal is sent, and wherein the first channel occurs contemporaneous with the command signal.

23. The network interface as recited in claim 22 , wherein the sync signal comprises a byte of information coded to signal the start of a frame of data comprising at least the first and second series of bytes.

24. The network interface as recited in claim 22 , further comprising N data pins, where the sync signal comprises a pulse synchronized by a clock signal sent from the network interface, wherein the sync signal is sent across the signal pin contemporaneous with M coded bits sent across the N data pins to signal the start of a frame of data.

25. The network interface as recited in claim 22 , wherein M equals eight.

26. The network interface as recited in claim 22 , further comprising N data pins, where the command signal comprises a pulse synchronized by a clock signal sent from the network interface, wherein the command signal is sent across the signal pin contemporaneous with M coded bits sent across the N data pins to signal the start of a packet of data.

27. The network interface as recited in claim 26 , wherein M equals eight.

28. The network interface as recited in claim 22 , wherein the command signal comprises a code having a logic low voltage value at the most significant bit location.

29. The network interface as recited in claim 22 , wherein the sync signal comprises a code of hexadecimal FF.

30. The network interface as recited in claim 22 , further comprising a clock pin adapted to send a clock, and wherein the sync signal, command signal and the first and second series of bytes are synchronized to the clock.

31. A method for transmitting data, comprising:

receiving a frame of data sent from a network of interconnected multimedia devices;

partitioning the frame of data into timeslots;

forwarding the partitioned data into respective plurality of channels selected according to time-divisional multiplexing;

signaling the start of a first channel within the plurality of channels with a start of frame byte; and

signaling the start of a packet of data within one of the plurality of channels with a start of packet byte.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
MERGER Recorded Dec 11, 2017
From: STANDARD MICROSYSTEMS CORPORATION
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 044820/0715 →