Negative differential resistance (NDR) based memory device with reduced body effects
A memory device (such as an SRAM) using negative differential resistance (NDR) elements is disclosed. Body effect performances for NDR FETs (and other FETs) that may be used in such device are enhanced by floating a body of some/all the NDR FETs. Various embodiments using common or separate wells for such elements are illustrated to achieve superior body effect performance results, including a silicon-on-insulator (SOI) implementation.
1. A memory device comprising:
a data transfer element adapted to facilitate a read operation or a write operation involving a storage node of the memory cell; and
a first negative differential resistance (NDR) element coupled to said data transfer element, said storage node and a first voltage potential, wherein said first NDR element is adapted to operate with a first NDR characteristic between said storage node and said first voltage potential; and
a second NDR element coupled to said first NDR element, said data transfer element, said storage node and a second voltage potential wherein said second NDR element is adapted to operate with a second NDR characteristic between said storage node and said second voltage potential;
said data transfer element, said first NDR element and said second NDR element are located within a single common well situated in a silicon based substrate, said single common well being doped with a first type of dopant that is opposite to a second type of dopant used in said silicon based substrate;
wherein said single common well is biased so as to float a body region of said data transfer element, said first NDR element and said second NDR element.
2. The memory device of claim 1 , wherein said memory device is a static random access memory (SRAM) cell.
3. The memory device of claim 1 , wherein p-type dopant is used for said single common well.
4. The memory device of claim 1 , wherein said storage node includes a common region shared by said transfer FET, said first NDR element and said second NDR element.
5. The memory device of claim 1 , wherein said data transfer element is a field effect transistor (FET) and said first NDR element and said second NDR element are NDR-capable FETs.
6. The memory device of claim 5 , wherein a body effect is substantially reduced for said NDR capable FETs.
7. A memory device comprising:
a transfer field effect transistor (FET) adapted to facilitate a read operation or a write operation involving a storage node of the memory device; and
wherein said transfer FET is located within a first well situated in a silicon based substrate, said first well being doped with a first type of dopant that is opposite to a second type of dopant used in said silicon based substrate;
a first negative differential resistance (NDR) element coupled to said transfer FET, said storage node and a first voltage potential, wherein said first NDR element is adapted to operate with a first NDR characteristic between said storage node and said first voltage potential; and
a second NDR element coupled to said first NDR element, said transfer FET, said storage node and a second voltage potential wherein said second NDR element is adapted to operate with a second NDR characteristic between said storage node and said second voltage potential;
wherein said first NDR element and said second NDR element are located within a second well situated separately from said first well in said silicon based substrate, said second well also being doped with said first type of dopant;
further wherein at least said second well is biased so as to float a body region of said first NDR element and said second NDR element to reduce body effects.
8. The memory device of claim 7 , wherein said memory device is a static random access memory (SRAM) cell.
9. The memory device of claim 7 , wherein p-type dopant is used for said single common well.
10. The memory device of claim 7 , wherein said storage node includes a common region shared by said first NDR element and said second NDR element, and which common region is connected by an conductive interconnect to a separate source/drain region for the transfer FET.
11. The memory device of claim 7 , wherein said first NDR element and said second NDR element are NDR capable FETs.
12. The memory device of claim 11 , wherein a body effect is substantially reduced for said NDR capable FETs.
13. A memory device comprising:
a transfer field effect transistor (FET) adapted to facilitate a read operation or a write operation involving a storage node of the memory cell; and
a first negative differential resistance (NDR) element coupled to said transfer FET, said storage node and a first voltage potential, wherein said first NDR element is adapted to operate with a first NDR characteristic between said storage node and said first voltage potential; and
wherein said transfer FET and said first NDR element are located within a first well situated in a silicon based substrate, said first well being doped with a first type of dopant that is opposite to a second type of dopant used in said silicon based substrate;
a second NDR element coupled to said first NDR element, said transfer FET, said storage node and a second voltage potential wherein said second NDR element is adapted to operate with a second NDR characteristic between said storage node and said second voltage potential;
wherein said second NDR element is located within a second well situated separately from said first well in said silicon based substrate, said second well also being doped with said first type of dopant;
further wherein at least said second well is biased so as to float a body region of said second NDR element to reduce body effects.
14. The memory device of claim 13 , wherein said memory device is a static random access memory (SRAM) cell.
15. The memory device of claim 13 , wherein p-type dopant is used for said single common well.
16. The memory device of claim 13 , wherein said storage node includes a common region shared by said transfer FET and said first NDR element, and which common region is connected by a conductive interconnect to a separate source/drain region for said second NDR element.
17. The memory device of claim 13 , wherein said first NDR element and said second NDR element are NDR capable FETs.
18. The memory device of claim 16 , wherein a body effect is substantially reduced for said second NDR capable FET.
19. In a memory device having three active elements, including a transfer field effect transistor (FET), a first negative differential resistance (NDR) element and a second NDR element that are operably interconnected to store a data value, the improvement comprising:
at least one of the first NDR element and the second NDR element being implemented as an NDR-capable FET that is located in a first Common well;
wherein the first common well can be biased so as to float a body region of the NDR capable FET and reduce a body effect of at least such NDR capable FET.
20. In a memory device having at most three active elements, including a transfer field effect transistor (FET), a first negative differential resistance (NDR) element and an NDR pull-up element that are operably interconnected to store a data value, the improvement comprising:
the pull up NDR element and the pull down NDR element both being implemented as NDR-capable FETs that are located in a first common well with the transfer gate;
wherein the first common well can be biased so as to float a body region of the NDR pull-up FET and reduce a body effect of at least such NDR pull-up FET.
21. In a memory device having at most three active elements, including a transfer field effect transistor (FET), a negative differential resistance (NDR) pull-down element and an NDR pull-up element that are operably interconnected to store a data value, the improvement comprising:
the pull-up NDR element and the pull-down NDR element both being implemented as NDR-capable FETs that are located in a first common well that is different from a second well in which the transfer gate is located;
wherein the first well can be biased so as to float a body region of the NDR pull-up FET and reduce a body effect of at least such NDR pull-up FET.
22. In a memory device having at most three active elements, including a transfer field effect transistor (FET), a negative differential resistance (NDR) pull-down element and an NDR pull-up element that are operably interconnected to store a data value, the improvement comprising:
the pull-up NDR element being implemented as an NDR-capable FET that is located in a first well that is different from a second well in which the NDR pull-down element and the transfer gate are located;
wherein the first well can be biased so as to float a body region of the NDR pull-up FET and reduce a body effect of at least such NDR pull-up FET.
23. In a silicon on insulator (SOI) based memory device having three active elements, including a transfer field effect transistor (FET), a first negative differential resistance (NDR) element and a second NDR element that are operably interconnected to store a data value, the improvement comprising:
at least one of the first NDR element and the second NDR element being implemented as a SOI-based NDR-capable FET.
wherein a contact is provided to a body region of the SOI-based NDR capable FET so as to provide a bias signal and operate the SOI based memory device in a non-floating body effect mode.
24. In a silicon on insulator (SOI) based memory device having three active elements, including a transfer field effect transistor (FET), a first negative differential resistance (NDR) element and a second NDR element that are operably interconnected to store a data value, the improvement comprising:
at least one of the first NDR element and the second NDR element being implemented as a SOI-based NDR-capable FET;
wherein a body region of the SOI-based NDR capable FET is floated so as to reduce a body effect.
25. The SOI based memory device of claim 24 , wherein during operation said body region can be fully depleted when said SOI-based NDR capable FET is turned on.
26. The SOI based memory device of claim 24 , wherein during operation said body region can only be partially depleted when said SOI-based NDR capable FET is turned on.
27. The SOI based memory device of claim 24 , further including a trapping layer located above said body region for effectuating said negative differential resistance.
28. The SOI based memory device of claim 24 , wherein exactly three active elements are used for each memory cell, and the transfer field effect transistor (FET), the first negative differential resistance (NDR) element and the second NDR element are all implemented in SOI form.