Patent Assignment
Reel/Frame 018837/0769
Assignment of Assignor's Interest
Recorded: 2006-12-21
Pages: 7
Assignor
PROGRESSANT TECHNOLOGIES, INC.
Executed: 2006-12-18
Assignee
SYNOPSYS, INC.
700 E. MIDDLEFIELD ROAD, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties
(63)
Negative Differential Resistance Field Effect Transistor (Ndr-Fet) & Circuits Using the Same
PCT:
PCT/US2002/041333 ↗
Memory Cell Utilizing Negative Differential Resistance Field-Effect Transistors
PCT:
PCT/US2002/041334 ↗
Negative Differential Resistance (Ndr) Element & Memory with Reduced Soft Error Rate
PCT:
PCT/US2003/019924 ↗
Enhanced Read & Write Methods for Negative Differential Resistance (Ndr) Based Memory Device
PCT:
PCT/US2003/019925 ↗
Adaptive Negative Differential Resistance Device
PCT:
PCT/US2003/040268 ↗
N-Channel Pull-Up Element & Logic Circuit
PCT:
PCT/US2003/040360 ↗
Variable Voltage Supply Bias and Methods for Negative Differential Resistance (Ndr) Based Memory Device
PCT:
PCT/US2005/044789 ↗
Cmos Compatible Process for Making a Tunable Negative Differential Resistance (Ndr) Device
Patent:
6,596,617 →
Application:
09/602,658 →
Cmos-Process Compatible, Tunable Ndr (Negative Differential Resistance) Device and Method of Operating Same
Patent:
6,512,274 →
Application:
09/603,101 →
Charge Trapping Device and Method for Implementing a Transistor Having a Negative Differential Resistance Mode
Patent:
6,479,862 →
Application:
09/603,102 →
Insulated-Gate Field-Effect Transistor Integrated with Negative Differential Resistance (Ndr) Fet
Negative Differential Resistance Field Effect Transistor (Ndr-Fet) & Circuits Using the Same
Charge Pump for Negative Differential Resistance Transistor
Dual Mode Fet & Logic Circuit Having Negative Differential Resistance Mode
Memory Cell Using Negative Differential Resistance Field Effect Transistors
Enhanced Read & Write Methods for Negative Differential Resistance (Ndr)Based Memory Device
Negative Differential Resistance (Ndr) Based Memory Device with Reduced Body Effects
Negative Differential Resistance (Ndr) Elements & Memory Device Using the Same
Negative Differential Resistance (Ndr) Element and Memory with Reduced Soft Error Rate
Patent:
6,567,292 →
Application:
10/185,569 →
Silicon on Insulator (Soi) Negative Differential Resistance (Ndr) Based Memory Device with Reduced Body Effects
Method for Making Both a Negative Differential Resistance (Ndr) Device and a Non-Ndr Device Using a Common Mos Process
Patent:
6,680,245 →
Application:
10/232,129 →
Charge Trapping Device and Method
Patent:
6,700,155 →
Application:
10/252,906 →
Negative Differential Resistance (Ndr) Element and Memory with Reduced Soft Error Rate
Patent:
6,727,548 →
Application:
10/298,700 →
Method of Orperating a Dual Mode Fet& Logic Circuit Having Negative Differential Resistance Mode
Patent:
6,664,601 →
Application:
10/298,726 →
Method for Fabricating a Dual Mode Fet & Logic Circuit Having Negative Differential Resistance Mode
Patent:
6,686,267 →
Application:
10/298,915 →
Field Effect Transistor Pull-Up/ Load Element
Patent:
6,724,024 →
Application:
10/298,916 →
Method for Configuring a Device to Include a Negative Differential Resistance (Ndr) Characteristic
Patent:
6,693,027 →
Application:
10/298,917 →
Charge Trapping Device & Method of Forming the Same
Method of Forming a Negative Differential Resistance Device
Process for Controlling Performance Characteristics of a Negative Differential Resistance (Ndr) Device
Negative Differential Resistance (Ndr) Device and Method of Operating Same
Patent:
6,686,631 →
Application:
10/315,741 →
Integrated Circuit Having Negative Differential Resistance (Ndr) Devices with Varied Peak-to-Valley Ratios (Pvrs)
Adaptive Negative Differential Resistance Device
Methods of Testing/Stressing a Charge Trapping Device
N-Channel Pull-Up Element & Logic Circuit
Charge Trapping Device
Cmos Compatible Process for Making a Charge Trapping Device
Variable Threshold Semiconductor Device and Method of Operating Same
Cmos Process Compatible, Tunable Negative Differential Resistance (Ndr) Device and Method of Operating Same
Negative Differential Resistance Pull Up Element
Patent:
6,894,327 →
Application:
10/827,713 →
Method of making memory cell utilizing negative differential resistance devices
Application:
10/827,787 →
Negative Differential Resistance Load Element
Patent:
6,933,548 →
Application:
10/827,886 →
Charge Trapping Pull Up Element
Patent:
6,956,262 →
Application:
10/828,356 →
Negative Differential Resistance (Ndr) Memory Device with Reduced Soft Error Rate
Patent:
6,853,035 →
Application:
10/831,867 →
Negative Differential Resistance (Ndr) Memory Cell with Reduced Soft Error Rate
Patent:
6,861,707 →
Application:
10/831,950 →
Insulated-Gate Field-Effect Transistor Integrated with Negative Differential Resistance (Ndr) Fet
Method of Making Memory Cell Utilizing Negative Differential Resistance Devices
Two Terminal Silicon Based Negative Differential Resistance Device
Methods of Testing/Stressing a Charge Trapping Device
Method of Making Adaptive Negative Differential Resistance Device
Process for Controlling Performance Characteristics of a Negative Differential Resistance (Ndr) Device
Charge Trapping Device and Method of Forming the Same
Enhanced Read and Write Methods for Negative Differential Resistance (Ndr) Based Memory Device
Negative differential resistance (NDR) memory device with reduced soft error rate
Application:
11/027,093 →
Publication:
US 2005/0145955
Silicon on Insulator (Soi) Negative Differential Resistance (Ndr) Based Memory Device with Reduced Body Effects
Method of Forming a Negative Differential Resistance Device
Method of Forming a Negative Differential Resistance Device
Negative Differential Resistance Field Effect Transistor for Implementing a Pull Up Element in a Memory Cell
Negative Differential Resistance (Ndr) Elements and Memory Device Using the Same
Variable Voltage Supply Bias and Methods for Negative Differential Resistance (Ndr) Based Memory Device
Compact Static Memory Cell with Non-Volatile Storage Capability
Stacked memory cell utilizing negative differential resistance devices
Application:
11/345,248 →
Publication:
US 2006/0125017
Charge Trapping Device
Application:
11/382,474 →
Publication:
US 2006/0197122
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.