CMOS compatible process for making a charge trapping device
A method of making an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that uses charge trapping for altering channel conductivity characteristics is disclosed. Other suitable and conventional processing steps are used to finalize completion of the fabrication of the charge trapping device so that the entire process is compatible and achieved with CMOS processing techniques, and so that non-charge trapping devices can be formed at the same time in a common sequence of manufacturing operations.
1. A method of forming a semiconductor circuit on a substrate comprising the steps of:
(a) forming a charge trapping device that operates with a charge trapping characteristic using a metal oxide semiconductor (MOS) process;
wherein said charge trapping device does not trap charge long enough so as to operate as a memory cell;
(b) forming a non-charge trapping device that operates without a charge trapping characteristic using said MOS process;
wherein at least portions of steps (a) and (b) are performed at the same time using a single common processing operation of said MOS process.
2. The method of claim 1 , wherein said single common processing operation includes a mask.
3. The method of claim 1 , wherein said single common processing operation includes an implant.
4. The method of claim 1 , wherein non-charge trap based logic circuits and memory circuits employing said charge trapping device are formed at the same time in a common substrate.
5. The method of claim 1 , wherein a channel region of said charge trapping device and a source/drain region of said second non-charge trapping device are formed by a common implant operation.
6. The method of claim 1 , further including a step: doping a channel region of said first charge trapping region with an impurity having an opposite conductivity to that of said substrate.
7. The method of claim 1 , wherein said charge trapping device is formed to include a negative differential resistance characteristic.
8. The method of claim 1 , wherein said charge trapping device is formed with a charge trapping layer integrated as part of a gate region of said charge trapping device.
9. The method of claim 8 , wherein said charge trapping layer includes a plurality of charge trapping sites distributed near an interface with a channel region of said charge trapping device.