Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET
A semiconductor device is disclosed that includes integrated insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance (NDR) field-effect transistor elements, combined and formed on a common substrate. Thus, a variety of circuits, including logic and memory are implemented with a combination of conventional and NDR capable FETs. Because both types of elements share a number of common features, they can be fabricated with common processing operations to achieve better integration in a manufacturing facility.
1. A method of fabricating a semiconductor device comprising the steps of:
(a) providing a semiconductor die;
(b) forming insulated gate field effect transistors (IGFETS) in and/or on said semiconductor die during a first set of operations;
(c) forming negative differential resistance field effect transistors (NDR-FETs) in and/or on said semiconductor die during a second set of processing operations,
wherein said first set of processing operations and said second set of processing operations include one or more common operations so that portions of some of said IGFETs and portions of at least some of said NDR FETs are formed at the same time during said one or more common operations
wherein an IGFET gate insulation layer is formed using a different set of processing operations than those used for forming an NDR FET gate insulation layer.
2. The method of claim 1 , wherein said IGFET gate insulation layer is substantially thinner than said NDR FET gate insulation layer.
3. The method of claim 1 , wherein at least a part of said NDR FET gate insulation layer is formed prior to said IGFET gate insulation layer.
4. The method of claim 1 , wherein said NDR FET gate insulation layer and said IGFET gate insulation layer include a common gate-dielectric layer, and said NDR FET gate insulation layer further includes an additional gate-dielectric layer.
5. The method of claim 4 further including a step of forming a charge trap layer within said additional gate-dielectric layer or at the interface between the gate insulating film and a channel of the NDR-FET.
6. The method of claim 5 further including a step of forming an additional common gate-dielectric layer over said additional gate-dielectric layer of said NDR FETs and said common gate-dielectric layer of said NDR FETs and IGFETs.
7. The method of claim 5 , wherein said charge trap layer is formed by implantation in regions of said NDR FETs and/or oxidation of doped channel regions of said NDR FETs.
8. The method of claim 7 , wherein said implantation uses boron, phosphorus, arsenic, fluorine, silicon, germanium, nitrogen or a metallic species.
9. A method of fabricating a semiconductor device comprising the steps of:
(a) providing a semiconductor die;
(b) forming insulated gate field effect transistors (IGFETs) in and/or on said semiconductor die during a first set of operations;
(c) forming negative differential resistance field effect transistors (NDR FETs) in and/or on said semiconductor die during a second set of processing operations,
wherein said first set of processing operations and said second set of processing operations include one or more common operations so that portions of some of said IGFETS and portions of at least some of said NDR FETs are formed at the same time during said one or more common operations,
wherein said first set of operations include a first implant operation for an IGFET threshold adjustment, and said second set of operations include a second implant operation for an NDR FET threshold adjustment, and further wherein said first implant operation and said second implant operation are performed separately.
10. The method of claim 9 , wherein said first implant operation and said second implant operation use different dopant species.
11. The method of claim 9 , wherein IGFET channel regions are formed with a substantially different doping profile than NDR FET channel regions.
12. A method of fabricating a semiconductor device comprising the steps of:
(a) providing a semiconductor die;
(b) forming insulated gate field effect transistors (IGFETs) in and/or on said semiconductor die during a first set of operations;
(c) forming negative differential resistance field effect transistors (NDR FETs) in and/or on said semiconductor die during a second set of processing operations,
wherein said first set of processing operations and said second set of processing operations include one or more common operations so that portions of some of said IGFETS and portions of at least some of said NDR FETs are formed at the same time during said one or more common operations,
wherein said second set of operations include a step of forming a charge trap layer for said NDR FETs within a gate insulating film or at the interface between said gate insulating film and a semiconductor channel of the NDR-FETs.