Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device
Static random access memory (SRAM) performance is enhanced through the use of appropriate latch strength control. For example, latch strength in an SRAM cell is increased during data store operations to reduce power dissipation and improve reliability. Latch strength can also be increased to improve read speed, while latch strength can be reduced to improve write speed. In an SRAM cell including at least a negative differential resistance (NDR) device as a pull-up element, this type of latch control can be achieved through appropriate biasing of the NDR device(s). For example, drain-to-source bias can be increased or decreased to increase or decrease, respectively, latch strength. Similarly, gate-to-source bias can be increased or decreased to increase or decrease, respectively, latch strength.
1. A method of operating a static random access memory (SRAM) cell, wherein the SRAM cell includes a latching circuit comprising a negative differential resistance (NDR) device connected to a storage node, the method comprising:
supplying a first voltage potential across the latching circuit while the SRAM cell is operating in a data storage mode; and
supplying a second voltage potential across the latching circuit during a write operation to the data storage node,
wherein a first NDR valley current for the NDR device when the first voltage potential is supplied across the latching circuit is less than a second NDR valley current for the NDR device when the second voltage potential is supplied across the latching circuit.
2. The method of claim 1 , wherein the first voltage potential is greater than the second voltage potential.
3. The method of claim 2 , wherein the NDR device comprises a first NDR field effect transistor (FET),
wherein the latching circuit further comprises a second NDR FET,
wherein a source of the first NDR FET is connected to the data storage node,
wherein a drain of the second NDR FET is connected to the data storage node,
wherein supplying the first voltage potential comprises supplying a first voltage to a drain of the first NDR FET and supplying a second voltage to a source of the second NDR FET, and
wherein supplying the second voltage potential comprises supplying a third voltage to the drain of the first NDR FET and supplying a fourth voltage to the source of the second NDR FET.
4. The method of claim 3 , wherein the first voltage is greater than the third voltage.
5. The method of claim 3 , wherein the second voltage is less than the fourth voltage.
6. The method of claim 4 , further comprising supplying a third voltage potential across the latching circuit during a read operation to the data storage node,
wherein a third NDR valley current for the first NDR FET when the third voltage potential is supplied across the latching circuit is less than the second NDR valley current.
7. The method of claim 6 , wherein the third voltage potential is greater than the second voltage potential.
8. The method of claim 6 , wherein the third voltage potential is equal to the first voltage potential.
9. A method for operating a static random access memory (SRAM) cell, the SRAM cell comprising a latch circuit for data storage, the method comprising:
adjusting the latch circuit to operate with a first latching strength while the SRAM cell is operating in a data storage mode; and
adjusting the latch circuit to operate with a second latching strength while the SRAM cell is operating in a data write mode,
wherein the first latching strength is greater than the second latching strength.
10. The method of claim 9 , wherein the latch circuit comprises a negative differential resistance (NDR) device connected to a data storage node,
wherein adjusting the latch circuit to operate with the first latching strength comprises supplying a first voltage potential across the latch circuit,
wherein adjusting the latch circuit to operate with the second latching strength comprises supplying a second voltage potential across the latch circuit, and
wherein a first NDR valley current for the NDR device when the first voltage potential is supplied across the latch circuit is less than a second NDR valley current for the NDR device when the second voltage potential is supplied across the latch circuit.
11. The method of claim 10 , wherein the first voltage potential is greater than the second voltage potential.
12. The method of claim 11 , wherein the NDR device comprises a first NDR field effect transistor (FET),
wherein the latch circuit further comprises a second NDR FET,
wherein a source of the first NDR FET is connected to the data storage node,
wherein a drain of the second NDR FET is connected to the data storage node,
wherein supplying the first voltage potential comprises supplying a first voltage to a drain of the first NDR FET and supplying a second voltage to a source of the second NDR FET, and
wherein supplying the second voltage potential comprises supplying a third voltage to the drain of the first NDR FET and supplying a fourth voltage to the source of the second NDR FET.
13. The method of claim 12 , wherein the first voltage is greater than the third voltage.
14. The method of claim 12 , wherein the second voltage is less than the fourth voltage.
15. The method of claim 9 , further comprising adjusting the latch circuit to operate with a third latching strength while the SRAM cell is operating in a data read mode,
wherein the third latching strength is greater than the second latching strength.
16. The method of claim 15 , wherein the latch circuit comprises a negative differential resistance (NDR) device connected to a data storage node,
wherein adjusting the latch circuit to operate with the first latching strength comprises supplying a first voltage potential across the latch circuit,
wherein adjusting the latch circuit to operate with the second latching strength comprises supplying a second voltage potential across the latch circuit, the first voltage potential being greater than the second voltage potential, and
wherein adjusting the latch circuit to operate with the third latching strength comprises supplying a third voltage potential across the latch circuit, the third voltage potential being greater than the second voltage potential.
17. The method of claim 16 , wherein the first voltage potential is equal to the third voltage potential.
18. The method of claim 9 , wherein the latch circuit comprises a negative differential resistance (NDR) device and a data storage node connected to a first conduction terminal of the NDR device,
wherein adjusting the latch circuit to operate with the first latching strength comprises applying a first gate bias to the NDR device,
wherein adjusting the latch circuit to operate with the second latching strength comprises supplying a second gate bias to the NDR device, and
wherein a first peak current for the NDR device when receiving the first gate bias is greater than a second peak current for the NDR device when receiving the second gate bias.
19. A memory circuit comprising:
a static random access memory (SRAM) cell comprising a latching circuit and a transfer element, the latching circuit comprising a negative differential resistance (NDR) element connected to a data storage node, and the transfer element being coupled between a bit line and the data storage node; and
a biasing circuit for supplying a first voltage potential across the latching circuit while the transfer element is turned off, and for supplying a second voltage potential across the latching circuit while the transfer element is transferring data from the bit line to the storage node,
wherein a first NDR valley current of the NDR element while the first voltage potential is supplied across the latching circuit is less than a second NDR valley current of the NDR element while the second voltage potential is supplied across the latching circuit.
20. The SRAM cell of claim 19 , wherein the first voltage potential is greater than the second voltage potential.
21. The SRAM cell of claim 20 , wherein the NDR element comprises a first NDR field effect transistor (FET).
22. The SRAM cell of claim 21 , wherein the latching circuit further comprises a second NDR FET,
wherein a source of the first NDR FET is connected to the data storage node, and
wherein a drain of the second NDR FET is connected to the data storage node.
23. The SRAM cell of claim 19 , wherein the biasing circuit further supplies a third voltage potential across the latching circuit while the transfer element is transferring data from the data storage node to the bit line, wherein a third NDR valley current of the NDR element while the third voltage potential is supplied across the latching circuit is less than the second NDR valley current.
24. The SRAM cell of claim 23 , wherein the first voltage potential is greater than the second voltage potential, and
wherein the third voltage potential is greater than the second voltage potential.