Method of forming a negative differential resistance device
A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a variety of NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (V NDR ) and related parameters are also disclosed.
1. In a charge-trap based negative differential resistance (NDR) element which operates with an NDR characteristic having a peak current and a valley current, the improvement comprising:
distributing charge traps in a trapping region of the NDR element with a concentration and energy adapted so as to impart a peak-to-valley current ratio (PVR) for the NDR element which exceeds ten (10) over a temperature range greater than 0° C. and spanning at least 50° C.
2. The NDR element of claim 1 , wherein said PVR varies by less than a factor of five in an operating temperature spanning 25° and 125°.
3. The NDR element of claim 1 , wherein said PVR exceeds 1000 in an operating temperature range spanning from 25° to 125°.
4. The NDR element of claim 1 , wherein said trapping region forms an interface with a channel of a field effect transistor associated with the NDR element.