IP Library Granted Patent US 7,067,873
Granted Patent B2
US 7,067,873 · App. 10/753,948 · Granted Jun 27, 2006

Charge trapping device

Assignee: Progressant Technologies, Inc.
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Quick Facts
Patent No.
US 7,067,873
App. No.
10/753,948
Granted
Jun 27, 2006
Kind
B2
Abstract

A silicon based semiconductor device and method uses charge trapping to alter a density of carriers available in a channel of a field effect transistor (FET) for conduction. The charge trapping mechanism can be controlled by a source-drain bias voltages applied to the FET, so that the device can be turned off through a control mechanism separate from a gate voltage.

Claims (13)

1. A method of operating a silicon based semiconductor device comprising the steps of:

(a) receiving a bias voltage across a channel region of the silicon based semiconductor device, said channel region being coupled to a source region and a drain region;

(b) trapping carriers in a dielectric layer located proximate to said channel region to cause a change in a density of carriers available for conduction in said channel region;

(c) adjusting said bias voltage to control a number of charge carriers removed by said dielectric layer from said channel region,

wherein the silicon based semiconductor device can be switched off using said bias voltage and without using a program and/or an erase cycle.

2. The method of claim 1 , further including a step:

applying a second bias voltage to a body of the silicon based semiconductor device to counter a trapping mechanism effect of said dielectric layer.

3. The method of claim 1 , wherein said channel region exhibits negative differential resistance.

4. The method of claim 1 , wherein conduction in said channel region can be continuously and dynamically varied between a negative differential resistance mode and a non-negative differential resistance mode.

5. The method of claim 1 , wherein said dielectric layer is configured such that said charge carriers are trapped only temporarily and such that a continuous trapping and detrapping mechanism is set up between said trapping layer and said channel region.

6. The method of claim 1 , wherein a threshold voltage of the silicon based semiconductor device is controlled by said bias voltage.

7. The method of claim 1 , wherein said silicon based semiconductor device also can be switched off using a gate bias voltage.

8. The method of claim 1 , wherein said silicon based semiconductor device is turned on using a separate gate bias voltage.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2006
From: PROGRESSANT TECHNOLOGIES, INC.
To: SYNOPSYS, INC.
Reel/Frame 018837/0769 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2004
From: KING, TSU-JAE; LIU, DAVID K.Y.
To: PROGRESSANT TECHNOLOGIES, INC.
Reel/Frame 014926/0849 →
Continuity (3)
Continuation 1025290600 · Sep 23, 2002
Continuation 0960310200 · Jun 22, 2000
Related Publication 20040145010A1 · Jul 29, 2004