Variable threshold semiconductor device and method of operating same

1. In a silicon based semiconductor transistor device which includes a gate, a source region, a drain region, and a channel region coupling the source region and drain region, the improvement comprising:

a dynamically adjustable threshold voltage associated with the silicon based semiconductor transistor device, and which dynamically adjustable threshold voltage is controlled at least in part using a bias voltage applied across the gate and source region ot the semiconductor transistor device,

wherein said dynamically adjustable threshold voltage is caused by a trapping and detrapping mechanism associated with charge carriers in a channel region of the silicon based semiconductor transistor device.

2. The silicon based semiconductor transistor device of claim 1 , further wherein said gate and source region are located on a silicon on insulator substrate.

3. The silicon based semiconductor transistor device of claim 1 , wherein said dynamically adjustable threshold voltage can be altered while the device is turned on.

4. A silicon based semiconductor field effect transistor (FET) which includes a gate, a source region, a drain region, and a channel region coupling the source region and drain region and comprising:

a channel conduction control region, which channel conduction control region is part of the FET gate and is adapted to generate a first electric field which controls a density of electrons available for conduction in the channel region of the FET;

wherein said first electric field operates to counter a movement of carriers into the channel region caused by a separate second electric field associated with a gate bias voltage applied to the FET;

and further wherein said threshold voltage can be dynamically adjusted during operation of the silicon based semiconductor device using said gate bias voltage.

5. The FET of claim 4 , wherein said first electric field generated by said channel conduction control region is controlled in part by said gate bias voltage.

6. The FET of claim 4 wherein said first electric field generated by said channel conduction control region is controlled in part by a drain bias voltage.

7. The FET of claim 4 , wherein said channel conduction control region is doped with an impurity type which is the same as a substrate region of the FET, and opposite to an impurity type used in said source region and said drain region.

8. A silicon based semiconductor field effect transistor (FET) which includes a gate, a source region containing a first dopant of a first conductivity type, a drain region also containing said first conductivity type dopant, and a channel region coupling the source region and drain region, comprising:

a channel conduction control region, which channel conduction control region is part of the gate and contains a second dopant opposite said first conductivity type, said channel conduction control region being responsive to a gate bias voltage applied to the FET, and operating to generate a first electric field which controls a density of electrons available for conduction in the channel region of the FET;

wherein said first electric field operates to counter conduction in the channel caused by a separate electric field resulting from the gate bias voltage applied to the FET;

wherein a threshold voltage of the FET can be dynamically adjusted during operation of the silicon based semiconductor device using said gate bias voltage.

9. The FET of claim 8 , wherein said FET can be operated with a negative differential resistance mode.

10. In a silicon based semiconductor transistor device which includes a gate, a source region, a drain region, and a channel region coupling the source region and drain region, the improvement comprising:

a dynamically adjustable threshold voltage associated with the silicon based semiconductor transistor device, and which threshold voltage is adjusted at least in part under control of a bias voltage applied across the source region and drain region of the semiconductor transistor device,

wherein said semiconductor transistor device can be operated with a negative differential resistance mode.

11. The silicon based semiconductor transistor device of claim 10 , wherein said bias voltage can be used to turn off said device independently of a gate bias voltage.

12. In a silicon based semiconductor transistor device which includes a gate, a source region, a drain region, and a channel region coupling the source region and drain region, the improvement comprising:

a dynamically adjustable threshold voltage associated with the silicon based semiconductor transistor device, and which threshold voltage is adjusted using a first bias voltage applied across the source region and drain region of the silicon based semiconductor transistor device, and a second bias voltage applied across the source region and gate of the silicon based semiconductor transistor.

13. The silicon based semiconductor transistor device of claim 12 , wherein said device can be operated with a negative differential resistance (NDR) mode in response to a separate NDR bias signal applied to the device.

14. The silicon based semiconductor transistor device of claim 12 , wherein said device is formed as part of a memory circuit.

15. The silicon based semiconductor transistor device of claim 12 , wherein said dynamically adjustable threshold voltage can be adjusted up or down at approximately the same rate.

16. A semiconductor device comprising:

a gate;

a source region;

a drain region;

a channel region coupling the source region and the drain region; and

a dielectric layer disposed between the gate and the channel region, the dielectric layer comprising a plurality of charge traps located in close proximity to an interface between the dielectric layer and the channel region,

wherein the channel region has a graded doping profile that provides a dopant concentration that peaks at a relatively small distance below the interface between the dielectric layer and the channel region.

17. The semiconductor device of claim 16 , wherein the dopant concentration in the channel region peaks at less than 30 nm below the interface between the dielectric layer and the channel region.

18. The semiconductor device of claim 16 , wherein the graded doping profile is sized to generate a vertical electric field in the channel region greater than 10 6 V/cm when the semiconductor device is turned on.

19. The semiconductor device of claim 16 , wherein the plurality of charge traps are located within 1.5 nm of the interface between the dielectric layer and the channel region.

20. The semiconductor device of claim 16 , wherein the drain region includes a lightly doped drain region at a junction between the channel region and the drain region.