Negative differential resistance (NDR) elements and memory device using the same
A two-terminal NDR device can be formed by coupling the gate and drain of an NDR-capable FET, such that the coupled gate and drain form a first terminal and the source of the NDR-capable FET forms the second terminal. By applying an appropriate body bias between the body and source of an NDR-capable FET configured in this manner, the NDR-capable FET can be forced to operate with a negative threshold voltage, thereby allowing the resulting two-terminal device to exhibit the desired NDR characteristics. This two-terminal device can, for example, be used as a load element in a static random access memory (SRAM) cell and various other circuits where the NDR behavior of the device would be beneficial.
1. A memory cell comprising:
a storage node;
a transfer field effect transistor (FET), said transfer FET being configured to connect a data line to the storage node in response to at least one of a write signal and a read signal; and
a first negative differential resistance (NDR) field effect transistor (FET), the first NDR FET comprising a first source coupled to the storage node, a first gate coupled to receive a first gate bias voltage, a first drain for receiving a first supply voltage, and a first body coupled to receive a first body bias voltage; and
a second NDR FET, the second NDR FET comprising a second source coupled to receive a second supply voltage, a second gate coupled to receive a second gate bias voltage, a second drain coupled to the storage node, and a second body coupled to receive a second body bias voltage,
wherein the first body bias voltage causes the first NDR FET to exhibit one of a zero threshold voltage and a negative threshold voltage.
2. The memory cell of claim 1 , wherein the first gate bias voltage is equal to the first supply voltage.
3. The memory cell of claim 1 , wherein a first channel doping concentration of the first NDR FET is substantially less than a second channel doping concentration of the second NDR FET.
4. The memory cell of claim 1 , wherein a first channel doping concentration of the first NDR FET is substantially equal to a second channel doping concentration of the second NDR FET.
5. The memory cell of claim 1 , wherein the first NDR FET, the second NDR FET, and the transfer FET share a common substrate and at least one common layer.
6. The memory cell of claim 5 , wherein the common substrate is a silicon on insulator (SOI) substrate.
7. The memory cell of claim 1 , wherein the storage node comprises a diffusion region shared by the first NDR FET and the second NDR FET as the first source and the second drain, respectively.
8. The memory cell of claim 7 , wherein the diffusion region forms one of a source and a drain for the transfer FET.
9. The memory cell of claim 1 , wherein said first NDR FET and second NDR FET both use a charge trapping region that is located at an interface between an insulation layer and a substrate for both the first NDR FET and the second NDR FET.
10. The memory cell of claim 1 , wherein said first NDR FET and second NDR FET use different types of charge trapping regions.
11. The memory cell of claim 1 , wherein the first body bias voltage and the second body bias voltage are equal to a common body bias voltage;
wherein the common body bias voltage is greater than the second supply voltage, and
wherein the common body bias voltage is no greater than 0.5 V.
12. A method of operating a memory cell having a storage node comprising the steps of:
biasing a first negative differential resistance (NDR) field effect transistor (FET) with a first gate bias voltage to allow the first NDR FET to be operated with a first NDR characteristic;
biasing a second NDR FET with a second gate bias voltage to allow the second NDR element to be operated with a second NDR characteristic;
coupling the first NDR FET and the second NDR FET in series to form a storage node at a junction between the first NDR FET and the second NDR FET;
supplying a first body bias voltage to a first body of the first NDR FET to cause the first NDR FET to exhibit one of a zero threshold voltage and a negative threshold voltage; and
operating the first NDR FET and the second NDR FET with the first NDR characteristic and the second NDR characteristic, respectively, to latch a data value at the storage node.
13. The method of claim 12 , further comprising:
supplying a first voltage to a first drain of the first NDR FET;
supplying a second voltage to a second source of the second NDR FET,
wherein the first gate bias voltage is equal to the first voltage.
14. The method of claim 13 , wherein the second gate bias voltage is equal to the first voltage.
15. The method of claim 13 , wherein the first body bias voltage is greater than the second voltage.
16. The method of claim 15 , further comprising supplying the first body bias voltage to a second body of the second NDR FET,
wherein the first body bias voltage is no greater than 0.5 V.