Instrument initiated communication for automatic test equipment

1. A circuit testing apparatus, comprising:

at least one test instrument;

a bus master circuit coupled to said at least one test instrument, said bus master circuit adapted to receive measure data from said at least one test instrument and, upon initiation from said at least one test instrument, to package the measure data to provide packaged data; and

a switching/processing circuit coupled to receive the packaged data from said bus master circuit, to process the packaged data to provide processed data, and adapted to communicate the processed data to a host computer.

2. The circuit testing apparatus of claim 1 , wherein the packaged data includes:

a data packet corresponding to the measure data; and

an extended header descriptor portion of the header associated with the data packet, the extended header descriptor including a processing identifier corresponding to a type of processing to be performed on the data packet.

3. The circuit testing apparatus of claim 1 , wherein said switching/processing circuit comprises:

a switching circuit coupled to said bus master circuit and adapted to route the packaged data; and

at least one processor coupled to the switching circuit, the at least one processor adapted to receive the packaged data and to process the packaged data to provide the processed data.

4. The circuit testing apparatus of claim 3 , wherein the at least one processor is adapted to receive the packaged data and to separate a data packet and an extended header descriptor from the packaged data, the at least one processor further adapted to process the data packet in response to the extended header descriptor to provide the processed data.

5. The circuit testing apparatus of claim 3 , wherein said switching/processing circuit further includes a first buffer memory coupled to the switching circuit.

6. The circuit testing apparatus of claim 5 , wherein the first buffer memory is coupled to the at least one processor.

7. The circuit testing apparatus of claim 1 , wherein said bus master circuit is coupled to a measure memory, the measure memory adapted to receive the measure data from said at least one test instrument and to provide the measure data to said bus master circuit.

8. The circuit testing apparatus of claim 1 , wherein the processed data includes binned data.

9. The circuit testing apparatus of claim 1 , wherein said bus master circuit and said switching/processing circuit are on separate circuit boards.

10. The circuit testing apparatus of claim 1 , wherein said bus master circuit and said switching/processing circuit are on one or more circuit boards included in the at least one test instrument.

11. A method for testing a device under test, comprising:

capturing measure data in a test instrument, the measure data corresponding to one or more functional tests of the device under test performed by the test instrument;

initiating, with the test instrument, operations upon the measure data, the operations including:

packaging the measure data with a bus master circuit as packaged data; and

transferring the packaged data to a switching/processing circuit.

12. The method of claim 11 , wherein the initiating further includes:

routing the packaged data to a processor within the switching/processing circuit; and

processing the packaged data with the processor to provide processed data.

13. The method of claim 12 , wherein the packaging includes packaging the measure data with the bus master circuit as packaged data, the packaged data including a data header, and wherein the processing includes processing the packaged data with the processor, the processing responsive to the header.

14. The method of claim 12 , wherein the processing comprises:

pre-determining pass and fail thresholds associated with the one or more functional tests; and

associating the data packet with the pass and fail thresholds to provide binned data.

15. The method of claim 12 , wherein the packaging includes:

generating a data packet corresponding to the measure data; and

generating an extended header descriptor associated with the data packet, the extended header descriptor including a processing identifier corresponding to a type of processing to be performed on the data packet.

16. An method of manufacturing an electronic circuit, comprising:

fabricating an electronic circuit; and

testing the electronic circuit with a circuit testing apparatus, wherein the testing comprises:

capturing measure data in a test instrument, the measure data corresponding to one or more functional tests of the electronic circuit performed by the test instrument;

initiating, with the test instrument, operations upon the measure data, the operations including:

packaging the measure data with a bus master circuit as packaged data; and

transferring the packaged data to a switching/processing circuit.

17. The method of claim 16 , wherein the initiating further includes:

routing the packaged data to a processor within the switching/processing circuit; and

processing the packaged data with the processor to provide processed data.

18. The method of claim 17 , wherein the packaging includes packaging the measure data with the bus master circuit as packaged data, the packaged data including a data header, and wherein the processing includes processing, the packaged data with the processor, the processing responsive to the header.

19. The method of claim 17 , wherein the processing comprises:

pre-determining pass and fail thresholds associated with the one or more functional tests; and

associating the data packet with the pass and fail thresholds to provide binned data.

20. The method of claim 17 , wherein the packaging includes:

generating a data packet corresponding to the measure data; and

generating an extended header descriptor associated with the data packet, the extended header descriptor including a processing identifier corresponding to a type of processing to be performed on the data packet.