Semiconductor memory device capable of applying stress voltage to bit line pair

1. A semiconductor memory device comprising:

a control circuit controlling a normal operation and a test operation of said semiconductor memory device;

a memory cell array having a plurality of memory cells arranged in rows and columns;

a plurality of bit line pairs provided to correspond to said columns of said memory cell array;

a plurality of data line pairs each provided to correspond to a predetermined number of said plurality of bit line pairs;

a write circuit operative in said normal operation in response to data provided external to said semiconductor memory device to be written, to drive a level in potential of said data line pair;

a test potential drive circuit controlled in said test operation by said control circuit to drive a level in potential of said data line pair instead of said write circuit; and

a column select circuit operative in said normal operation in response to an address signal and controlled in said test operation by said control circuit to select said column of said memory cells and transmitting said level in potential of said data line pair to said bit line pair corresponding to said selected column of said memory cells.

2. The device of claim 1 , wherein said column select circuit in said test operation selects simultaneously a plurality of said bit line pairs capable of coupling with a single one of said data line pairs.

3. The device of claim 1 , comprising:

a plurality of word lines provided to correspond to said rows of said memory cell array; and

a row select circuit operative in said normal operation in response to said address signal and controlled in said test operation by said control circuit to selectively activate said word line,

wherein said control circuit in said test operation continues to hold said plurality of word lines in an inactive state.

4. The device of claim 1 , wherein said memory cell array includes;

a regular memory cell array having a plurality of regular memory cells; and

a redundant memory cell column having a plurality of redundant memory cells selectable in place of said regular memory cell if said regular memory cell array has a defective memory cell,

wherein said column select circuit in said test operation selects simultaneously a plurality of said regular memory cell columns and said redundant memory cell column capable of coupling with a single one of said data line pairs.

5. The device of claim 1 , wherein:

said memory cell array is divided into a first memory cell column group including a plurality of first memory cell columns and a second memory cell column group including a plurality of second memory cell columns each sandwiched between said first memory cell columns;

said plurality of data line pairs includes a first data line pair provided common to a plurality of said first memory cell columns and a second data line pair provided common to a plurality of said second memory cell columns; and

said test potential driver circuit includes a first drive circuit operative in said test operation in response to said control circuit to drive a level of said first data line pair and a second drive circuit operative in said test operation in response to said control circuit to drive a level of said second data line pair.

6. The device of claim 5 , wherein said control circuit controls said level in potential driven by said first drive circuit and that in potential driven by said second drive circuit independently.

7. The device of claim 1 , further comprising a plurality of sense amplifiers provided to correspond to said bit line pair to amplify a difference in potential on said bit line pair, wherein:

said column select circuit includes a decode circuit operative in said normal operation in response to an address signal and controlled in said test operation by said control circuit to selectively activate a plurality of column select signals, and a plurality of transmission circuits provided to correspond to said bit line pair and selectively activated by a corresponding one of said plurality of column select signals to transmit said level in potential of said data line pair to said bit line pair corresponding to said selected column of said memory cells; and

said control circuit in said test operation activates alternately said plurality of transmission circuits corresponding to an adjacent one of said bit lines.

8. The device of claim 1 , further comprising a plurality of sense amplifiers provided to correspond to said bit line pair and controlled by said control circuit to receive at least a first power supply potential selectively to amplify a difference in potential on said bit line pair, wherein:

said column select circuit includes a decode circuit operative in said normal operation in response to an address signal and controlled in said test operation by said control circuit to selectively activate a plurality of column select signals, and a plurality of transmission circuits provided to correspond to said bit line pair and selectively activated by a corresponding one of said plurality of column select signals to transmit said level in potential of said data line pair to said bit line pair corresponding to said selected column of said memory cells; and

said control circuit said test operation controls said test potential drive circuit to couple a data line of said data line pair with a second power supply potential higher than said first power supply potential, activates said transmission circuit and supplies said sense amplifier with said first power supply potential.