IP Library Granted Patent US 7,477,649
Granted Patent B2
US 7,477,649 · App. 10/196,824 · Granted Jan 13, 2009

Active FIFO threshold adjustment

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Quick Facts
Patent No.
US 7,477,649
App. No.
10/196,824
Granted
Jan 13, 2009
Kind
B2
Abstract

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to store input data in response to a write pointer and present output data in response to a read pointer. The second circuit may be configured to generate a control signal in response to the write pointer, the read pointer and a type of an information packet containing the input data.

Claims (49)

1. An apparatus comprising:

a first circuit configured to store input data in response to a write pointer and present output data in response to a read pointer, wherein said first circuit is further configured to (i) determine a type of an information packet containing said input data based upon a type field of said information packet and (ii) generate a first control signal based upon said type; and

a second circuit configured to generate a second control signal in response to said write pointer, said read pointer, a predetermined threshold and said first control signal, wherein said second circuit is further configured to generate said second control signal having (i) a first state in response to said write pointer and said read pointer being separated by a distance determined by said predetermined threshold and said information packet being a first type and (ii) a second state in response to said information packet being a second type.

2. The apparatus according to claim 1 , wherein said first circuit comprises a first-in first-out memory and said second control signal comprises a flag.

3. The apparatus according to claim 1 , wherein said second control signal comprises an almost full flag.

4. The apparatus according to claim 1 , wherein said apparatus is configured to control a data flow in response to said second control signal.

5. The apparatus according to claim 1 , wherein said input data comprises one or more types of information packets having predetermined sizes.

6. The apparatus according to claim 5 , wherein said information packets comprise information indicative of said predetermined sizes.

7. The apparatus according to claim 6 , wherein said first circuit is further configured to generate said first control signal in response to said information indicative of said predetermined sizes.

8. The apparatus according to claim 1 , wherein:

said first circuit comprises (i) a first-in, first-out (FIFO) memory configured to store said input data in response to said write pointer and present said output data in response to said read pointer and (ii) a detector circuit configured to generate said first control signal in response to said type field of said information packet containing said input data.

9. The apparatus according to claim 1 , wherein said second control signal comprises a handshaking signal of a communication channel.

10. The apparatus according to claim 9 , wherein said communication channel comprises a link of a storage area network (SAN).

11. The apparatus according to claim 9 , wherein said communication channel comprises a link between a storage device and a controller.

12. A method for actively adjusting a threshold of a first-in, first-out (FIFO) memory comprising the steps of:

receiving an information packet containing input data;

determining a type of said information packet;

storing said input data in response to a write pointer;

presenting output data in response to a read pointer; and

generating a control signal in response to said write pointer, said read pointer, a predetermined threshold and said type of said information packet containing said input data, wherein said control signal is generated having (i) a first state in response to said write pointer and said read pointer being separated by a distance determined by said predetermined threshold when said information packet comprises a data frame information structure type payload and (ii) a second state when said information packet comprises a non-data frame information structure type payload.

13. The method according to claim 12 , wherein said determining step further comprises the step of:

detecting a field of said information packet indicative of a size of said information packet.

14. The method according to claim 13 , wherein said generating step further comprises the step of:

enabling said control signal when said information packet size is larger than a predetermined size; and

disabling said control signal when said information packet size is smaller than said predetermined size.

15. The method according to claim 13 , wherein said generating step further comprises the step of:

enabling said control signal when said information packet size is larger than a latency of said input data; and

disabling said control signal when said information packet size is smaller than a latency of said input data.

16. The method according to claim 12 , further comprising the step of:

controlling a flow of one or more information packets on a communication channel in response to said control signal.

17. The method according to claim 12 , wherein said generating step further comprises:

controlling the state of said control signal in response to a type field of said information packet.

18. The method according to claim 17 , wherein said controlling step comprises:

enabling said control signal in response to one or more types of information packets.

19. The method according to claim 17 , wherein said controlling step comprises:

inhibiting said control signal in response to one or more types of information packets.

20. The method according to claim 12 , wherein said control signal comprises an almost full flag.

21. A method for actively adjusting a threshold of a first-in, first-out (FIFO) memory comprising the steps of:

receiving an information packet containing input data;

determining a type of said information packet based upon detecting a field of said information packet indicative of a size of said information packet;

storing said input data in response to a write pointer;

presenting output data in response to a read pointer; and

generating a control signal in response to said write pointer, said read pointer, a predetermined threshold and said type of said information packet containing said input data, wherein said control signal is enabled when said information packet size is larger than a predetermined size and disabled when said information packet size is smaller than said predetermined size.

22. A method for actively adjusting a threshold of a first-in, first-out (FIFO) memory comprising the steps of:

receiving an information packet containing input data;

determining a type of said information packet based upon detecting a field of said information packet indicative of a size of said information packet;

storing said input data in response to a write pointer;

presenting output data in response to a read pointer; and

generating a control signal in response to said write pointer, said read pointer, a predetermined threshold and said type of said information packet containing said input data, wherein said control signal is enabled when said information packet size is larger than a latency of said input data and disabled when said information packet size is smaller than a latency of said input data.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER PREVIOUSLY RECORDED AT REEL: 047357 FRAME: 0302. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0658. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
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Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
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TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
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CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →