Granted Patent B1

US 7,111,123 · App. 10/202,526 · Granted Sep 19, 2006

Abstract

Claims (50)

1. A priority encoder for receiving a plurality of input signals and from said input signals generating output signals in accordance with an alterable priority sequence, said priority encoder comprising:

a plurality of input circuits to receive said input signals from a content addressable memory (CAM) array;

a CAM array word line decoder coupled to the CAM array that accesses locations of the CAM array and generates at least one priority transformation signal in response to a received address value;

a priority setting circuit for receiving the at least one priority transformation signal that indicates a priority index for modification of said priority sequence;

an encoding circuit in communication with said plurality of input circuits and said priority setting circuit for generating said output signals in accordance with said priority sequence; and

an enabling circuit for receiving an enabling signal and for communicating said enabling signal to said encoding circuit, such that upon deactivation of said enabling signal, said encoding circuit generates said output signals in accordance with said priority sequence with no modification by said priority setting circuit.

2. The priority encoder circuit of claim 1 wherein said input signals are match signals of the CAM array and said priority index indicates a region of said CAM array exempted from effective comparison.

3. The priority encoder circuit of claim 2 wherein said priority index is an index address of said CAM array determined with a previous search of said content addressable memory and applied to the CAM array word line decoder.

4. The priority encoder of claim 1 wherein said CAM array word line decoder has a first mode for providing word line addresses to said CAM array and a second mode for providing said priority index to said priority setting circuit.

5. A circuit for restricting a search space in a content addressable memory, comprising a content addressable memory (CAM) array word line decoder that receives an incoming index and provides a decoded output to an encoder circuit, wherein said CAM array word line decoder is a word line decoder for said content addressable memory and has a first mode for accessing locations of a CAM array by activating word lines of the CAM array and a second mode for providing said priority index to said priority setting circuit in response to the incoming index value.

6. The circuit of claim 5 further comprising:

a plurality of input circuits to receive match signals from said content addressable memory; and

a priority setting circuit for receiving the decoded output indicating a priority index for modification of a priority sequence of said search space from said incoming index.

7. The circuit of claim 5 wherein said encoder is in communication with said plurality of input circuits and said priority setting circuit for generating an output index signal in accordance with said priority sequence indicating a match location within said CAM array.

8. The circuit of claim 7 further comprises an enabling circuit for receiving an enabling signal and for communicating said enabling signal to said priority setting circuit and said encoder, such that upon deactivation of said enabling signal, said encoder generates said output index signal in accordance with said priority sequence with no modification by said priority setting circuit.

9. The circuit of claim 6 wherein said priority index indicates a region of said CAM array exempted from effective comparison.

10. The circuit of claim 5 wherein said incoming index is an index address of said CAM array determined with a previous search of said CAM array.

11. A method for restricting a search space in a content addressable memory, comprising the steps of:

searching said content addressable memory (CAM) to create a first match result index according to a first prioritization of the CAM;

setting the first match result index to define a restricted address space of said CAM to form a second prioritization of the CAM;

after searching said CAM to create the first match result index, searching said CAM according to the second prioritization of the CAM; and

disallowing match result addresses of said CAM outside of said restricted address space.

12. The method of claim 11 further comprising the steps of:

setting a priority of said match result addresses;

after disallowing match result addresses of said CAM outside of said restricted address space, in the event of match result, selecting at least one match result address from within the restricted search space and according to the priority; and

creating an output index from said selected match result address.

13. The method of claim 11 wherein said priority index indicates a region of said CAM exempted from effective comparison.

14. The method of claim 11 wherein setting said highest priority index includes the steps of:

receiving said highest priority index by a word line decoder of said CAM;

said word line decoder performing the steps of:

operating in a first mode, said first mode comprising the step of decoding word line addresses for said CAM, and

operating in a second mode, said second mode comprising said step of decoding said highest priority index to set said restricted address space.

15. An apparatus for restricting a search space in a content addressable memory, comprising:

means for setting a highest priority index to define a restricted address space of said content addressable memory, said means for setting the highest priority index including means for receiving said highest priority index by a word line decoder of said content addressable memory that accesses searchable locations of the content addressable memory;

means for searching said content addressable memory; and

means for disallowing match result addresses of said content addressable memory outside of said restricted address space.

16. The apparatus of claim 15 further comprising:

means for setting a priority of said match result addresses;

means for selecting said match result addresses; and

means for creating an output index from said match result address.

17. The apparatus of claim 15 wherein said priority index indicates a region of said content addressable memory exempted from effective comparison.

18. The apparatus of claim 15 wherein said highest priority index is an index address of said content addressable memory determined with a previous search of said content addressable memory.

19. The apparatus of claim 16 wherein said means for creating said output index comprises:

means for searching said content addressable memory to create a first match result address having a highest priority; and

means for setting said first match result address as said highest priority index to constrain said restricted address space;

wherein means for creating said output index functions repeatedly to create multiple output indices.

20. The apparatus of claim 15 wherein:

said word line decoder performs the steps of:

operating in a first mode, said first mode comprising the step of decoding word line addresses for said content addressable memory, and

operating in a second mode, said second mode comprising said step of decoding said highest priority index to set said restricted address space.

Assignments (12)