Method and apparatus for debugging a data processing system
View Patent ↗A data processing system ( 10 ) includes a CPU ( 12 ) and debug circuitry ( 16 ). CPU ( 12 ) can execute instructions which provide direct input to one or more of trigger circuitry ( 32 ), multi-function debug counters ( 34 ), combining logic ( 36 ), and action select and control logic ( 38 ). Breakpoints can be cascaded, and separate breakpoint sequences can be triggered from a same trigger. A selected trigger ( 117 ) can produce a resulting action or trigger ( 119 ) but only if it occurs in a predetermined order compared to one or more other triggers ( 117 ). Multi-function debug counters ( 34 ) can perform a wide variety of programmable functions, can be started and stopped using the same or separate triggers, and can be optionally concatenated with each other.
1. A data processing system, comprising:
a central processing unit coupled to a bus for receiving instructions including a first debug instruction; and
a debug circuit, comprising:
registers for being loaded with set-up data, wherein the set-up data comprises breakpoint addresses and counter preload values;
trigger circuitry coupled to the registers and the central processing unit, counter circuitry coupled to the registers and the central processing unit, and combining logic coupled to the registers and to the trigger circuitry;
wherein the counter circuitry is configurable to either count triggers from breakpoint matches or count clock periods;
wherein the central processing unit is characterized as providing a debug communication signal in response to the first debug instruction to at least one of the trigger circuitry, the counter circuitry, and the combining logic; and
wherein the combining logic is for using information from the registers to direct the combining of information from the debug communication signal, the trigger circuitry, and the counter circuitry to generate valid triggers.
2. The data processing system of claim 1 , further comprising action select and control logic coupled to the combining logic wherein the bus is further characterized as providing a debug halt instruction to the central processing unit and the central processing unit is further characterized as providing a halt signal to the action select and control logic in response to receiving the debug halt instruction.
3. The data processing system of claim 2 , wherein the first debug instruction is a debug action select instruction, and the action select and control logic responds to the debug action select instruction by altering an action of the action select and control logic.
4. The data processing system of claim 1 , wherein the first debug instruction is a debug event instruction, the debug communication signal is coupled to the combining logic, and the combining logic provides a complex trigger as one of the valid triggers.
5. The data processing system of claim 4 , wherein the debug circuit further comprises action select and control logic that provides a first debug action in response to the complex trigger.
6. The data processing system of claim 4 , wherein the counter circuitry performs at least one of a start and stop in response to the complex trigger.
7. The data processing system of claim 1 , wherein the first debug instruction is a debug event instruction coupled to the counter circuitry, and the counter circuitry performs at least one of a start and stop in response to the debug event instruction.
8. The data processing system of 1 , wherein the first debug instruction is a DEBUGCTR ON instruction, the debug communication signal is coupled to the counter circuitry, and the counter circuitry turns on in response to the DEBUGCTR ON instruction.
9. The data processing system of claim 1 , wherein the first debug instruction is a DEBUGCTR OFF instruction, the debug communication signal is coupled to the counter circuitry, and the counter circuitry turns off in response to the DEBUGCTR OFF instruction.
10. The data processing system of claim 1 , wherein the first debug instruction is a DEBUGCTR HALT instruction, the debug communication signal is coupled to the counter circuitry, and the counter circuitry is prevented from restarting in response to the DEBUGCTR HALT instruction.
11. The data processing system of claim 1 , wherein the first debug instruction is a DEBUGCTR RELOAD instruction, the debug communication signal is coupled to the counter circuitry, and the counter circuitry is reloaded in response to the DEBUGCTR RELOAD instruction.
12. The data processing system of claim 1 , further comprising a trace history buffer coupled to the counter circuitry, wherein the first debug instruction is a DEBUGCTR TO-TRACE instruction, the debug communication signal is coupled to the counter circuitry, and the trace history buffer is loaded with the contents of the counter circuitry in response to the DEBUGCTR TO-TRACE instruction.
13. The data processing system of claim 1 , further comprising transmit and receive circuitry coupled to the counter circuitry, wherein the first debug instruction is a DEBUGCTR TO-TX instruction, the debug communication signal is coupled to the counter circuitry, and the transmit and receive circuitry is loaded with the contents of the counter circuitry in response to the DEBUGCTR TO-TX instruction.
14. A data processing system, comprising:
a central processing unit coupled to a bus for receiving instructions including a first debug instruction; and
a debug circuit, comprising:
registers for being loaded with set-up data, wherein the set-up data comprises breakpoint addresses and counter preload values;
a debug port resource comprising transmit and receive circuitry coupled to the registers and to the central processing unit and a counter coupled to the registers and to the central processing unit, wherein the debug port resource is for using information from the registers to direct the combining of information from the counter and the central processing unit;
wherein the counter is configurable to either count triggers from breakpoint matches or count clock periods; and
wherein the central processing unit is characterized as providing a debug communication signal in response to the first debug instruction for selectively enabling or disabling at least one of the transmit and receive circuitry and the counter.
15. The data processing system of claim 14 , wherein the counter is characterized as having contents and wherein the first debug instruction is further characterized as being for routing the contents of the counter to the debug port resource.
16. The data processing system of claim 14 , wherein the counter is coupled to the bus and starts counting in response to a first command from the central processing unit and stops counting in response to a second command from the central processing unit.