Granted Patent
Utility
US 6,617,873
· Confirmation No. 6960
SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD THEREOF
Inventor:
Koichi Yokomizo
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2003-07-15 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2003-07-15 | LET. |
Miscellaneous Incoming Letter | 1 | View | |
| 2002-08-15 | TRNA |
Transmittal of New Application | 4 | View | |
| 2002-08-15 | A.PE |
Preliminary Amendment | 7 | View | |
| 2002-08-15 | SPEC |
Specification | 39 | View | |
| 2002-08-15 | CLM |
Claims | 4 | View | |
| 2002-08-15 | ABST |
Abstract | 1 | View | |
| 2002-08-15 | DRW |
Drawings-only black and white line drawings | 9 | View | |
| 2002-08-15 | OATH |
Oath or Declaration filed | 3 | View |
Inventors
Koichi Yokomizo
Tokyo, JAPAN
Attorneys & Agents of Record
Classification
USPC
324/769
G01R31/2884
Prosecution
- Examiner
- KERVEROS, DEMETRIOS C
- Art Unit
- 2858
- Docket No.
- OKI.098D2
- Confirmation No.
- 6960
Foreign Priority
351578/98
·
1998-12-10
·
JAPAN
Publication
- Pub. No.
- US20020190744A1
- Pub. Date
- 2002-12-19
Patent Term Adjustment
-26days
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Quick Facts
- Patent No.
- US 6,617,873
- App. No.
- 10/218,617
- Filed
- 2002-08-15
- Granted
- 2003-09-09
- Pub. No.
- US20020190744A1
- Examiner
- KERVEROS, DEMETRIOS C
- Art Unit
- 2858
- PTA
- -26 days
External Links