High speed, low current consumption FIFO circuit
A FIFO circuit includes a write counter circuit, a memory circuit, a read counter circuit and a selector circuit. The write counter circuit counts a write clock signal during a valid period of input data, and outputs a write counter value. The memory circuit stores the input data in response to the write counter value. The read counter circuit counts a read clock signal when a decision is made that the memory circuit includes data that has not yet been read out, and outputs a read counter value. The read selector circuit reads data from the memory circuit in response to the read counter value. A small scale FIFO circuit can be obtained.
1. A FIFO circuit comprising:
a write counter circuit for counting a write clock signal during a valid period of input data, and for outputting a write counter value;
a memory circuit for storing the input data in response to the write counter value output from said write counter circuit;
an empty address management circuit for deciding whether said memory circuit includes data which has not yet been read out of said memory circuit, in response to the write counter value output from said write counter circuit and in response to a read counter value;
a read counter circuit for counting a read clock signal and for outputting the read counter value when said empty address management circuit makes a decision that said memory circuit includes the data which has not yet been read;
a selector circuit for selecting and reading data from said memory circuit in response to the read counter value output from said read counter circuit;
a write pulse generating circuit for converting the write counter value output from said write counter circuit into write pulses, wherein said memory circuit stores the input data in response to the write pulses output from said write pulse generating circuit; and
a delay circuit for delaying the input data to synchronize the input data with the write pulses, and for supplying the delayed input data to said memory circuit.
2. The FIFO circuit according to claim 1 , wherein said empty address management circuit manages a part of all the empty addresses comprising a plurality of discrete or continuous bits of the write counter value and read counter value.
3. The FIFO circuit according to claim 1 , wherein write pulses correspond to a number of bits of an address of the memory circuit.
4. A FIFO circuit comprising:
a write counter circuit for counting a write clock signal during a valid period of input data, and for outputting a write counter value;
a memory circuit for storing the input data in response to the write counter value output from said write counter circuit;
an empty address management circuit for deciding whether said memory circuit includes data which has not yet been read out of said memory circuit, in response to the write counter value output from said write counter circuit and in response to a read counter value;
a read counter circuit for counting a read clock signal and for outputting the read counter value when said empty address management circuit makes a decision that said memory circuit includes the data which has not yet been read;
a selector circuit for selecting and reading data from said memory circuit in response to the read counter value output from said read counter circuit, wherein said selector circuit is composed of a plurality of stages of selector circuits with a hierarchical configuration including pre-stage selector circuits that constitute an anticipatory selection circuit that enables outputs of said pre-stage selector circuits to be determined at least up to a timing of an immediately previous read clock pulse; and
a write pulse generating circuit for converting the write counter value output from said write counter circuit into write pulses, wherein said memory circuit stores the input data in response to the write pulses output from said write pulse generating circuit.
5. The FIFO circuit according to claim 4 , wherein said read counter circuit comprises a plurality of stages of counter circuits with a hierarchical structure, and wherein said FIFO circuit further comprises OR circuits for outputting logical ORs of outputs of said plurality of stages of counter circuits to generate selection signals of said plurality of stages of selector circuits.