Fault tolerant operation of reconfigurable devices utilizing an adjustable system clock
View Patent ↗A method of fault tolerant operation of an adaptive computing system includes identifying a faulty resource in a signal path of the adaptive computing system, reconfiguring the signal path to avoid the faulty resource, estimating a time delay created by reconfiguring the signal path, and adjusting a system clock period to accommodate the time delay. In a preferred embodiment, an FPGA is configured into an initial self-testing area and a working area. Resources located within the self-testing area are tested and faulty resources identified. The FPGA is then reconfigured to avoid the identified faulty resources. When the resources are reconfigured for fault tolerant operation, signal path delays may be introduced into the system. If the signal path delays are in a critical path, a period of a system clock may be adjusted in order to insure proper fault tolerant operation.
1. A method of fault tolerant operation of a field programmable gate array during normal on-line operation comprising the steps of:
configuring said field programmable gate array into an initial self-testing area and a working area, said working area maintaining normal operation of the field programmable gate array;
identifying at least one faulty resource in a signal path of said self-testing area;
reconfiguring said signal path to exclude said at least one faulty resource;
estimating a propagation delay created by reconfiguring the signal path; and
adjusting a system clock period if the estimated propagation delay is greater than a critical path propagation delay.
2. The method of fault tolerant operation of a field programmable gate array set forth in claim 1 , wherein the step of identifying at least one faulty resource includes testing resources located within said initial self-testing area for faults.
3. The method of fault tolerant operation of a field programmable gate array set forth in claim 2 , wherein said testing step includes establishing resources within said self-testing area as a test pattern generator, an output response analyzer, and equivalently configured programmable logic blocks under test, applying test patterns generated by said test pattern generator to said programmable logic blocks under test, comparing outputs of said programmable logic blocks under test with said output response analyzer, and producing fault status data for said programmable logic blocks under test.
4. The method of fault tolerant operation of a field programmable gate array set forth in claim 2 , wherein said testing step includes establishing resources within said self-testing area as a test pattern generator, an output response analyzer, and at least two groups of wires under test, propagating test patterns generated by said test pattern generator along said at least two groups of wires under test, comparing outputs of said at least two groups of wires under test with said output response analyzer, and producing fault status data for said at least two groups of wires under test.
5. The method of fault tolerant operation of a field programmable gate array set forth in claim 1 further comprising allocating at least one resource of the field programmable gate array as a spare; and
wherein the reconfiguring step includes determining a new configuration of at least the signal path determined to include the at least one faulty resource utilizing the at least one spare resource to replace the at least one faulty resource.
6. The method of fault tolerant operation of a field programmable gate array set forth in claim 1 further comprising the step of roving said initial self-testing area by reconfiguring said field programmable gate array such that a portion of said working area becomes a subsequent self-testing area and at least a portion of said initial self-testing area becomes a portion of said working area.
7. The method of fault tolerant operation of a field programmable gate array set forth in claim 1 , wherein said initial self-testing area includes at least two self-testing areas.
8. The method of fault tolerant operation of a field programmable gate array set forth in claim 1 further comprising the step of comparing the estimated propagation delay created by reconfiguring the signal path to the critical path propagation delay.
9. The method of fault tolerant operation of a field programmable gate array set forth in claim 1 further comprising the step of calculating an adjusted system clock period using actual timing data from the reconfigured signal path.
10. The method of fault tolerant operation of a field programmable gate array set forth in claim 9 , wherein the step of identifying at least one faulty resource includes testing resources located within said initial self-testing area for faults.
11. The method of fault tolerant operation of a field programmable gate array set forth in claim 10 , wherein said testing step includes establishing resources within said self-testing area as a test pattern generator, an output response analyzer, and equivalently configured programmable logic blocks under test, applying test patterns generated by said test pattern generator to said programmable logic blocks under test, comparing outputs of said programmable logic blocks under test with said output response analyzer, and producing fault status data for said programmable logic blocks under test.
12. The method of fault tolerant operation of a field programmable gate array set forth in claim 10 , wherein said testing step includes establishing resources within said self-testing area as a test pattern generator, an output response analyzer, and at least two groups of wires under test, propagating test patterns generated by said test pattern generator along said at least two groups of wires under test, comparing outputs of said at least two groups of wires under test with said output response analyzer, and producing fault status data for said at least two groups of wires under test.
13. The method of fault tolerant operation of a field programmable gate array set forth in claim 9 further comprising allocating at least one resource of the field programmable gate array as a spare; and
wherein the reconfiguring step includes determining a new configuration of at least the signal path determined to include the at least one faulty resource utilizing the at least one spare resource to replace the at least one faulty resource.
14. The method of fault tolerant operation of a field programmable gate array set forth in claim 9 further comprising the step of roving said initial self-testing area by reconfiguring said field programmable gate array such that a portion of said working area becomes a subsequent self-testing area and at least a portion of said initial self-testing area becomes a portion of said working area.
15. The method of fault tolerant operation of a field programmable gate array set forth in claim 9 , wherein said initial self-testing area includes at least two self-testing areas.
16. A method of fault tolerant operation of an adaptive computing system comprising the steps of:
identifying at least one faulty resource in a signal path of said adaptive computing system;
reconfiguring said signal path to avoid said at least one faulty resource;
estimating a time delay created by reconfiguring the signal path; and
adjusting a system clock period to accommodate said estimated time delay.
17. The method of fault tolerant operation of an adaptive computing system set forth in claim 16 further comprising the step of comparing the time delay created by reconfiguring the signal path to a critical path time delay, and adjusting the system clock period if the time delay created by reconfiguring the signal path is larger than the critical path time delay.
18. The method of fault tolerant operation of an adaptive computing system set forth in claim 17 further comprising the step of determining an adjusted system clock period using actual timing data from the reconfigured signal path.
19. The method of fault tolerant operation of an adaptive computing system set forth in claim 17 , wherein the adaptive computing system includes at least one field programmable gate array configured into an initial self-testing area and a working area, said working area maintaining normal operation of the field programmable gate array; and
wherein the step of identifying at least one faulty resource includes testing resources within said initial self-testing area.
20. The method of fault tolerant operation of an adaptive computing system set forth in claim 17 further comprising allocating at least one resource of the adaptive computing system as a spare; and
wherein the reconfiguring step includes determining a new configuration of at least the signal path determined to include the at least one faulty resource utilizing the at least one spare resource to replace the at least one faulty resource.
21. An apparatus for testing resources during normal on-line operation of a field programmable gate array comprising:
a system clock in communication with said field programmable gate array; and
a controller in communication with said field programmable gate array (a) for configuring said field programmable gate array into an initial self-testing area and a working area, said working area maintaining normal operation of the field programmable gate array, (b) for identifying at least one faulty resource in a signal path of said self-testing area, (c) for reconfiguring said signal path to avoid said at least one faulty resource, (d) for estimating a propagation delay created by reconfiguring the signal path, and (e) for adjusting a period of said system clock if the estimated propagation delay is greater than the critical path propagation delay.
22. The apparatus for testing resources during normal on-line operation of a field programmable gate array set forth in claim 21 , wherein said controller further compares the estimated propagation delay created by reconfiguring the signal path to the critical path propagation delay.
23. The apparatus for testing resources during normal on-line operation of a field programmable gate array set forth in claim 21 , wherein the controller calculates the adjusted system clock period using actual timing data from the reconfigured signal path.