System and method of acquiring delay, setup and hold values for integrated circuit cells
View Patent ↗The method of the present invention acquires delay, setup and hold values that appropriately reflect the timing characteristics of an integrated circuit represented by a cell file. A data and clock input slope pair is selected and the data setup time value is swept with respect to the clock. For each setup value a corresponding hold value is determined for functional failure. Then for each setup and hold value pair a delay value is ascertained. In one exemplary implementation optimal delay, setup and hold values are determined and utilized to facilitate higher frequency designs using the same physical cell layout library.
1. A timing acquisition method comprising:
choosing a dock input slope value and data input slope value;
establishing a plurality of setup time values for said clock input slope value and data input slope value;
determining a hold time value corresponding to each of said plurality of setup time values for functional failure; and
determining a clock transition to output transition delay value for each pair of said plurality of said setup time values and said hold time values.
2. A timing acquisition method of claim 1 further comprising making a decision if additional delay values are desired.
3. A timing acquisition method of claim 2 further comprising examining if a change in delay values exceeds a desired percentage change.
4. A timing acquisition method of claim 2 further comprising analyzing if a current delay value minus a previous delay value is less than a particular percentage.
5. A timing acquisition method of claim 2 further comprising changing each of said plurality of setup time values.
6. A timing acquisition method of claim 2 further comprising choosing a load value.
7. A timing acquisition method of claim 1 further comprising determining timing values corresponding to a minimum sequence time.
8. A timing acquisition method of claim 7 further comprising determining a delay and setup value pair that result in a minimal sum.
9. A timing acquisition method of claim 8 further comprising recording as optimal a delay value, setup value and hold value that correspond to said delay and setup value pair that results in a minimal sum.
10. A timing acquisition method of claim 8 further comprising performing separate iterations of said timing acquisition method to acquire the delay, setup and hold values for each sequential component separately.
11. A timing acquisition method of claim 8 further comprising determining a delay value for varying loads using said optimal setup and hold pair.
12. A timing acquisition method comprising:
selecting a clock and data signal input slope;
sweeping a data setup time through a plurality of data setup time values with respect to the clock;
determining a hold time value for each of said plurality of setup time values; and
determining a delay through a cell for each of said plurality of setup time values and said corresponding hold time values.
13. A timing acquisition method of claim 12 further comprising running a transistor level simulation to determine said delay.
14. A timing acquisition method of claim 12 wherein said delay is determined for varying loads.
15. A timing acquisition method of claim 12 further comprising identifying an optimal delay, setup and hold triplet.
16. A timing acquisition method of claim 15 wherein said optimal delay, setup and hold triplet is selected by analyzing the sum of delay and setup values pairs to determine a minimum and then recording a corresponding delay, setup and hold values.
17. A timing acquisition method of claim 12 wherein optimal delay setup and hold values are utilized to facilitate high frequency designs using the same physical cell layout library.
18. A computer usable medium having a computer readable program code embodied therein for causing a computer system to perform a timing acquisition method comprising:
choosing a clock input slope value and data input slope value;
establishing a plurality of setup time values for said clock input slope value and data input slope value;
determining a hold time value corresponding to each of said plurality of setup time values for functional failure; and
determining a clock transition to output transition delay value for each pair of said plurality of said setup time values and said hold time values.
19. A computer usable medium with timing acquisition method instructions of claim 18 further comprising choosing a different load value, a clock input slope value and data input slope value.
20. A computer usable medium with timing acquisition method instructions of claim 18 wherein said optimal delay setup and hold values are utilized to facilitate high frequency designs using the same physical cell layout library.