IP Library Granted Patent US 7,219,187
Granted Patent B1
US 7,219,187 · App. 10/232,576 · Granted May 15, 2007

Search parameter table in a content addressable memory

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Quick Facts
Patent No.
US 7,219,187
App. No.
10/232,576
Granted
May 15, 2007
Kind
B1
Abstract

A content addressable memory device having a search parameter table.

Claims (77)

1. A content addressable memory (CAM) device, comprising:

a plurality of CAM blocks;

a search parameter table coupled to the plurality of CAM blocks to store a plurality of search parameters, wherein the search parameter table comprises a plurality of registers; and

circuitry to select one of the plurality of registers based on a selection code provided in association with a compare instruction, wherein each of the plurality of registers includes storage for at least one CAM table identifier that identifies a table, within one or more of the CAM blocks, that is to be searched in a compare operation.

2. The CAM device of claim 1 , further comprising:

an instruction decoder; and

a search parameter table decoder coupled to the instruction decoder and the search parameter table, the search parameter table decoder including the circuitry to select the one of the plurality of registers based on the selection code.

3. The CAM device of claim 1 , wherein each of the plurality of CAM blocks comprises:

a CAM array;

drivers coupled to the CAM array; and

a block select circuit coupled to the search parameter table and the drivers.

4. The CAM device of claim 3 , wherein each of the plurality of CAM blocks further comprises:

a plurality of global mask registers coupled to the drivers; and

a global mask select circuit coupled to the plurality of global mask registers and the block select circuit.

5. The CAM device of claim 1 , further comprising:

a device index generator coupled to the CAM blocks; and

device flag logic coupled to the CAM blocks.

6. The CAM device of claim 1 , wherein the search parameters comprise global mask register identifiers.

7. The CAM device of claim 1 , further comprising a plurality of filter circuits coupled to the plurality of CAM blocks.

8. The CAM device of claim 4 , wherein the global mask select circuit comprises:

a select circuit; and

a decoder coupled to the select circuit.

9. The CAM device of claim 3 , wherein the block select circuit comprises:

a storage element to store a table identifier;

a plurality of compare circuits coupled to the storage element; and

a logic gate coupled to the plurality of compare circuits.

10. The CAM device of claim 1 , wherein each of the plurality of CAM blocks comprises:

a plurality of CAM arrays each coupled to a corresponding match enabling logic; and

a plurality of block select circuits coupled to the search parameter table, each of the plurality of block select circuits coupled to one of the corresponding match enabling logic.

11. The CAM device of claim 10 , wherein each of the plurality of CAM blocks further comprises:

drivers coupled to the plurality of CAM arrays;

a plurality of global mask registers coupled to the drivers; and

a global mask select circuit coupled to the search parameter table and the plurality of global mask registers.

12. The CAM device of claim 11 , wherein each of the plurality of CAM blocks further comprises a select circuit coupled to the plurality of block select circuits and the global mask select circuit.

13. A method, comprising:

receiving a selection code in a content addressable memory (CAM) device in association with a compare instruction, the CAM device having a plurality of CAM blocks;

selecting one of a plurality of registers based on the selection code, wherein each of the plurality of registers includes storage for at least one CAM table identifier that identifies a table, within one or more of the CAM blocks, that is to be searched in one or more compare operations.

14. The method of claim 13 , further comprising pre-programming the search parameters into a search parameter table.

15. The method of claim 14 , wherein pre-programming comprises storing the search parameters in the one of the plurality of registers.

16. The method of claim 13 , further comprising selecting, based on the selection code, one of a plurality of global masks to be used in the compare operation.

17. The method of claim 13 , further comprising enabling the one or more of the CAM blocks to be searched in the compare operation.

18. The method of claim 13 , further comprising performing the compare operation concurrently with at least one other compare operation.

19. A method, comprising:

pre-programming a plurality of search parameters into respective registers of a search parameter table within a content addressable memory (CAM) device, each of the registers having storage for at least a first number of bits;

selecting one of the search parameters using a selection code having fewer bits than the first number of bits;

performing a plurality of concurrent compare operations in the CAM device using one or more of a plurality of CAM blocks identified by the selected one of the search parameters, wherein performing the plurality of concurrent compare operations comprises performing the plurality of concurrent compare operations in the CAM device based on the selected one of the search parameters; and

wherein one of the compare operations is performed using a global mask identified by the selected one of the search parameters.

20. An apparatus, comprising:

a search parameter table having a plurality of registers to store search parameters;

means for receiving a selection code in a content addressable memory (CAM) device in association with a compare instruction, the CAM device having a plurality of CAM blocks; and

means for selecting one of the plurality of registers based on the selection code, wherein each of the plurality of registers includes storage for at least one CAM table identifier that identifies a table, within one or more of the CAM blocks, that is to be searched in a compare operation.

21. The apparatus of claim 20 , further comprising means for selecting one of a plurality of global masks to be used in the compare operation.

22. The apparatus of claim 21 , further comprising means for selecting one of the plurality of CAM blocks to be used in one of the compare operations.

23. The apparatus of claim 22 , further comprising means for concurrently performing the compare operation concurrently with at least one other compare operation.

24. The apparatus of claim 20 , further comprising means for generating a comparand from input data to be used in the compare operation.

25. A content addressable memory (CAM) device, comprising:

a plurality of CAM blocks;

a search parameter table to store a plurality of table identifiers that correspond to respective lookup tables within the plurality of CAM blocks;

circuitry to select at least one of the table identifiers based on a selection code received in association with a compare instruction; and

circuitry to compare the at least one of the table identifiers with values associated with the CAM blocks to selectively enable the CAM blocks to participate in a compare operation.

26. The CAM device of claim 25 , wherein each of the CAM blocks comprises a plurality of CAM arrays.

27. The CAM device of claim 25 , wherein at least two of the lookup tables are stored, at least in part, in one of the CAM blocks.

28. The CAM device of claim 25 , wherein at least one of the lookup tables is stored within two or more of the CAM blocks.

29. The CAM device of claim 25 , wherein the search parameter table comprises a plurality of registers, each of the registers including storage for one or more of the table identifiers.

30. The CAM device of claim 25 , wherein the values associated with the CAM blocks indicate a logical size of the CAM blocks.

31. The CAM device of claim 25 , wherein the values associated with the CAM blocks indicate a type of data stored in the CAM blocks.

32. The CAM device of claim 25 , wherein the values associated with the CAM blocks indicate a physical address of the CAM blocks.

33. A method of operation within a content addressable memory (CAM) device having a plurality of CAM blocks, the method comprising:

storing, in a search parameter table, a plurality of table identifiers that correspond to respective lookup tables within the plurality of CAM blocks;

selecting at least a first one of the table identifiers based on a selection code received in association with a compare instruction; and

comparing the first one of the table identifiers with values associated with the CAM blocks to selectively enable the CAM blocks to participate in a compare operation.

34. The method of claim 33 , wherein selecting comprises decoding the selection code.

35. The method of claim 33 , further comprising pre-programming the table identifiers into the search parameter table.

36. The method of claim 35 , wherein pre-programming the table identifiers into the search parameter table comprises storing the table identifiers in one of a plurality of registers within the search parameter table.

37. The method of claim 33 , wherein comparing the first one of the table identifiers with values associated with the CAM blocks comprises comparing the first one of the table identifiers with a value that indicates a logical size of one of the CAM blocks.

38. The method of claim 33 , wherein comparing the first one of the table identifiers with values associated with the CAM blocks comprises comparing the first one of the table identifiers with a value that indicates a type of data stored in one of the CAM blocks.

39. The method of claim 33 , wherein comparing the first one of the table identifiers with values associated with the CAM blocks comprises comparing the first one of the table identifiers with a value that indicates a physical address of one of the CAM blocks.

Assignments (12)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
RELEASE Recorded Sep 27, 2010
From: SILICON VALLEY BANK
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 025077/0977 →
SECURITY AGREEMENT Recorded Jul 17, 2009
From: NETLOGIC MICROSYSTEMS, INC.; NETLOGIC MICROSYSTEMS INTERNATIONAL LIMITED; NETLOGIC MICROSYSTEMS CAYMANS LIMITED
To: SILICON VALLEY BANK
Reel/Frame 022973/0710 →
RELEASE Recorded Oct 20, 2006
From: SILICON VALLEY BANK
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 018420/0760 →
SECURITY AGREEMENT Recorded Apr 19, 2004
From: NETLOGIC MICROSYSTEMS, INC.
To: SILICON VALLEY BANK
Reel/Frame 015201/0812 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2002
From: KHANNA, SANDEEP; MCDERMOTT, JAMES P.
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 013264/0011 →