High speed sampling receiver with reduced output impedance
View Patent ↗A sampling receiver includes: at least one slave latch circuit; and at least one master latch circuit which further includes: at least one differential input transistor pair, and at least one bistable circuit. Output terminals of the at least one differential input transistor pair and output terminals of the at least one bistable circuit are coupled to the at least one slave latch circuit but in parallel to each other with reference to the at least one slave latch circuit for the purpose of reducing an output impedance to allow the sampling receiver to exhibit a high speed latch operation.
1. A sampling receiver comprising:
a slave latch circuit; and
first and second master latch circuits coupled to said slave latch circuit, said first and second master latch circuits performing a voltage level conversion of input signals and supplying level converted master latch signals to said slave latch circuit,
wherein said first master latch circuit comprises:
a first differential input transistor pair comprising a first pair of first conductivity type channel field effect transistors each having a respective output terminal coupled to said slave latch circuit, and
a first bistable circuit comprising first and second CMOS inverters each having a respective output terminal connected to said output terminal of a corresponding one of said first pair of first conductivity type channel field effect transistors of said first differential input transistor pair for outputting a respective one of said level-converted master latch signals,
wherein said second master latch circuit comprises:
a second differential input transistor pair comprising a second pair of second conductivity type, different form said first conductivity type, channel field effect transistors each having a respective output terminal coupled to said slave latch circuit; and
a second bistable circuit comprising a pair of third and fourth CMOS inverters each having a respective output terminal connected to said output terminal of a corresponding one of said second pair of second conductivity type channel field effect transistors of said, second differential input transistor pair for outputting another respective one of said level-converted master latch signals.
wherein said first and second differential input transistor pairs receive said input signals.
2. The sampling receiver as claimed in claim 1 , further including:
a first cross-coupled inverter circuit comprising first and second inverters coupled between said output terminal of said first CMOS inverter of said first master latch circuit and said output terminal of said third CMOS inverter of said second master latch circuit; and
a second cross-coupled inverter circuit comprising third and fourth inverters coupled between said output terminal of said second CMOS inverter of said first master latch circuit and said output terminal of said fourth CMOS inverter of said second master latch circuit.
3. The sampling receiver as claimed in claim 2 , wherein said slave latch circuit comprises a differential set/reset flip-flop circuit which includes:
a set terminal coupled to said output terminal of said first CMOS inverter of said first master latch circuit;
a reset terminal coupled to said output terminal of said second CMOS inverter of said first master latch circuit;
an inversion set terminal coupled to said output terminal of said third CMOS inverter of said second master latch circuit; and
an inversion reset terminal coupled to said output terminal of said fourth CMOS inverter of said second master latch circuit.
4. The sampling receiver as claimed in claim 1 , wherein said first differential input transistor pair of said first master latch circuit receives a first drive current from a first current-supplying first conductivity type channel field effect transistor which is controlled by a first clock signal, and said second differential input transistor pair of said second master latch circuit receives a second drive current from a second current-supplying second conductivity type channel field effect transistor which is controlled by a second clock signal.
5. The sampling receiver as claimed in claim 1 , wherein said first and second master latch circuits are enabled by first and second clock signals, respectively, and said first and second clock signals take different states which are inverted to each other.
6. The sampling receiver as claimed in claim 5 , wherein when said first and second master latch circuits are enabled, one of said first and second master latch circuits is placed in latch-operable state over any common mode levels of input signals.
7. A sampling receiver comprising:
first and second master latch circuits for Performing a voltage level conversion of input signals and supplying level-converted master latch signals from respective master latch circuit output terminals,
wherein said first master latch circuit comprises:
a first differential input transistor pair comprising a first pair of first conductivity type channel field effect transistors each having a respective output terminal coupled to a corresponding one of said master latch circuit output terminals, and
a first bistable circuit comprising first and second CMOS inverters each having a respective output terminal connected to said output terminal of a corresponding one of said first pair of first conductivity type channel field effect transistors of said first differential input transistor pair for outputting a respective one of said level-converted master latch signals,
wherein said second master latch circuit comprises:
a second differential input transistor pair comprising a second pair of second conductivity type, different form said first conductivity type, channel field effect transistors each having a respective output terminal coupled to another corresponding one of said master latch circuit output terminals; and
a second bistable circuit compromising a pair of third and fourth CMOS inverters each having a respective output terminal connected to said output terminal of a corresponding one of said second pair of second conductivity type channel field effect transistors of said second differential input transistor pair for outputting another respective one of said level-converted master latch signals.
8. The latch circuit as claimed in claim 7 , wherein said first differential input transistor pair of said first master latch circuit receives a first drive current from a first current-supplying first conductivity type channel field effect transistor which is controlled by a first clock signal, and said second differential input transistor pair of said second master latch circuit receives a second drive current from a second current-supplying second conductivity type channel field effect transistor which is controlled by a second clock signal.
9. The latch circuit as claimed in claim 7 , wherein said first and second master latch circuits are enabled by first and second clock signals, respectively, and said first and second clock signals take different states which are inverted to each other.
10. The latch circuit as claimed in claim 9 , wherein when said first and second master latch circuits are enabled, one of said first and second master latch circuits is placed in latch-operable state over any common mode levels of input signals.