Circuit generating constant narrow-pulse-width bipolarity cycle monocycles using CMOS circuits
View Patent ↗A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputs clock signals varying in time based upon the data. The pulse generating circuit is coupled to the multiplexer, receives the clock signals and generates a first series of pulses including an up-pulse preceding a down-pulse, or a second series of pulses including a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer. The buffer circuit is coupled to the pulse generating circuit and includes a switch circuit and a common mode buffer. The switch circuit generates the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit. The common mode buffer circuit is coupled to the switching circuit and reduces noise generated by the switch circuit.
1. A mono-cycle generating circuit comprising:
a multiplexer receiving data, determining whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputting clock signals;
a pulse generating circuit, coupled to the multiplexer, receiving the clock signals and generating a first series of pulses comprising an up-pulse preceding a down-pulse, or a second series of pulses comprising a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer; and
a buffer circuit, coupled to the pulse generating circuit, comprising:
a switch circuit generating the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit, and
a common mode buffer circuit coupled to the switching circuit and reducing noise generated by the switch circuit.
2. The mono-cycle generating circuit as in claim 1 , wherein the multiplexer outputs the clock signals having delay or no delay, based upon the data.
3. The mono-cycle generating circuit as in claim 1 , wherein the pulse generating circuit comprises complementary sets of transistors generating the up-pulse and the down-pulse.
4. The mono-cycle generating circuit as in claim 1 , wherein the switch circuit comprises:
a first switch comprising a PMOS transistor coupled to a source vottage,
a second switch comprising an NMOS transistor coupled to the first switch through an AC coupling and to ground,
a third switch comprising a PMOS transistor coupled to the source voltage, and a fourth switch comprising an NMOS transistor coupled to the third switch and to ground.
5. The mono-cycle generating circuit as in claim 4 , wherein the common mode buffer circuit comprises complementary sets of amplifiers, the output of each of which is coupled to she switch circuit.
6. The mono-cycle generating circuit as in claim 5 , wherein the third switch is coupled to the fourth switch through a complementary set of transistors, and the gates of each of the transistors of the complementary set of transistors is coupled to the output of respective amplifiers of the common mode buffer circuit.
7. The mono-cycle generating circuit as in claim 6 , wherein the respective output of each of the amplifiers is coupled to a gate of a second set of complementary transistors, and each set of complementary transistors forms mirror copies.
8. The mono-cycle generating circuit as in claim 1 , said multiplexer generating the first series of pulses and the second series of pulses by interjecting delay into clock pulses received by the multiplexer circuit.
9. The mono-cycle generating circuit as in claim 1 , said pulse generating circuit comprising:
a NOR gate comprising complementary sets of transistors, and
a NAND gate comprising complementary sets of transistors.
10. A circuit comprising:
a multiplexer inputting a differential clock and data and outputting control signals based upon the data;
a down-pulse generating circuit, coupled to the multiplexer, comprising a NAND gate generating a down-pulse based upon the control signals;
an up-pulse generating circuit, coupled to thc multiplexer, comprising a NOR gate generating an up-pulse based upon the control signals;
an up-and-down pulse generating circuit, coupled to the multiplexer, comprising a NAND gate and a NOR gate, and generating an up-pulse and a down-pulse based upon the control signals; and
a driver circuit, coupled to the down-pulse generating circuit, to the up-pulse generating circuit, and to the up-and-down pulse generating circuit, generating mono-cycles based upon the up-pulse and the down-pulse.
11. The circuit as in claim 10 , wherein the driver circuit generates one of a positive mono-cycle and a negative mono-cycle in response to the data received by the multiplexer.
12. The circuit as in claim 10 , said driver circuit comprising:
a switch circuit generating one of a positive mono-cycle and a negative mono-cycle responsive to the control signals, and
a common mode buffer, coupled to the switch circuit, reducing current dissipation of the switch circuit.
13. The circuit as in claim 12 , wherein the switch circuit comprises current mirrors.
14. The circuit as in claim 12 , wherein the switch circuit comprises sets of switches, each set of switches comprising an NMOS and a PMOS transistor coupled to each other through an AC coupling.
15. The circuit as in claim 14 , wherein each transistor of one of the sets of transistors forms a current mirror with other transistors, and each transistor of the other of the sets of transistors is coupled to the common mode buffer.
16. The circuit as in claim 15 , wherein the common mode buffer comprises amplifiers coupled to the switch circuit.