Granted Patent
Utility
US 6,674,314
· Confirmation No. 1822
INTERPOLATING CIRCUIT, DLL CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
Inventor:
Yasuhiro Takai
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⬇ PDF
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Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2003-11-17 | IFEE |
Issue Fee Payment (PTO-85B) | 1 | View | |
| 2002-09-12 | TRNA |
Transmittal of New Application | 1 | View | |
| 2002-09-12 | SPEC |
Specification | 53 | View | |
| 2002-09-12 | CLM |
Claims | 14 | View | |
| 2002-09-12 | ABST |
Abstract | 1 | View | |
| 2002-09-12 | DRW |
Drawings-only black and white line drawings | 15 | View | |
| 2002-09-12 | OATH |
Oath or Declaration filed | 2 | View |
Inventors
Yasuhiro Takai
Tokyo, JAPAN
Attorneys & Agents of Record
Classification
USPC
327/158
G11C8/00
H03K5/131
H03K5/133
H03K5/15046
H03L7/0814
H03L7/0816
H03L7/0818
H03L7/089
Prosecution
- Examiner
- LAM, TUAN THIEU
- Art Unit
- 2816
- Customer No.
- 27667
- Docket No.
- ELPIDA NEG-261
- Confirmation No.
- 1822
Foreign Priority
2001-285508
·
2001-09-19
·
JAPAN
Publication
- Pub. No.
- US20030052718A1
- Pub. Date
- 2003-03-20
Patent Term Adjustment
0days
No related applications found.
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2018-08-21
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Quick Facts
- Patent No.
- US 6,674,314
- App. No.
- 10/241,986
- Filed
- 2002-09-12
- Granted
- 2004-01-06
- Pub. No.
- US20030052718A1
- Examiner
- LAM, TUAN THIEU
- Art Unit
- 2816
- PTA
- 0 days
External Links