Avoiding shorting in capacitors

1. A capacitor structure comprising:

a capacitor including

a top electrode,

a bottom electrode,

a capacitor dielectric layer between the top and bottom electrodes,

wherein the capacitor includes an upper and a lower portion, the demarcation of the upper and lower portion is between top and bottom surfaces of the capacitor dielectric layer; and

a dielectric sidewall spacer covering capacitor sidewalls in the upper portion of the capacitor, the dielectric sidewall spacer serves as a self-aligned etch mask for forming the lower portion of the capacitor, wherein the sidewall spacer creates a discontinuity in conductive fence that can form during patterning of the capacitor to prevent shorting of the electrodes.

2. The capacitor structure of claim 1 further comprises a bottom electrode plug electrically coupled to the bottom electrode and to a first diffusion region of a transistor, the capacitor and transistor forming a memory cell of a memory array.

3. The capacitor structure of claim 1 further comprises a bottom electrode plug electrically coupled to a common bottom electrode of a capacitor pair and to a common first diffusion region of first and second transistors, the capacitor pair and transistors form a memory cell pair of a portion of a group of cells arranged in a series architecture, a plurality of groups are interconnected to form a memory array.

4. The capacitor structure of claim 1 wherein the capacitor comprises a ferroelectric capacitor wherein the capacitor dielectric layer comprises a ferroelectric material.

5. The capacitor structure of claim 4 further comprises a bottom electrode plug electrically coupled to the bottom electrode and to a first diffusion region of a transistor, the capacitor and transistor forming a memory cell of a memory array.

6. The capacitor structure of claim 4 further comprises a bottom electrode plug electrically coupled to a common bottom electrode of a capacitor pair and to a common first diffusion region of first and second transistors, the capacitor pair and transistors form a memory cell pair of a portion of a group of cells arranged in a series architecture, a plurality of groups are interconnected to form a memory array.

7. The capacitor structure of any one of claims 1 - 6 wherein the demarcation between the upper and lower portions of the capacitors prevent shorting of the electrodes.

8. A capacitor structure comprising:

a capacitor including

a top electrode,

a bottom electrode,

a capacitor dielectric layer between the top and bottom electrodes,

wherein the capacitor includes an upper and a lower portion, the upper and lower portion whose demarcation is between top and bottom surfaces of the capacitor dielectric layer, the demarcation between the upper and lower portions of the capacitors prevent shorting of the electrodes by conductive fence which can form during processing, wherein the demarcation between the upper and lower portions is located at least 3 nm from the bottom surface of the capacitor dielectric layer; and

a dielectric sidewall spacer covering capacitor sidewalls in the upper portion of the capacitor.

9. The capacitor structure of claim 8 wherein the demarcation between the upper and lower portions is located about 5-10 nm from the bottom surface of the capacitor dielectric layer.

10. The capacitor structure of claim 7 wherein the dielectric sidewall spacer comprises a dielectric material selected from the group comprising oxides, nitrides, aluminum oxide or combination thereof.

11. A capacitor structure comprising:

a capacitor including

a top electrode,

a bottom electrode,

a capacitor dielectric layer between the top and bottom electrodes,

wherein the capacitor includes an upper and a lower portion, the upper and lower portion whose demarcation is between top and bottom surfaces of the capacitor dielectric layer, the demarcation between the upper and lower portions of the capacitors prevent shorting of the electrodes by conductive fence which can form during processing, wherein the demarcation between the upper and lower portions is located at least 3 nm from the top and bottom surfaces of the capacitor dielectric layer; and

a dielectric sidewall spacer covering capacitor sidewalls in the upper portion of the capacitor, the dielectric sidewall spacer comprises a dielectric material selected from the group comprising oxides, nitrides, aluminum oxide or combination thereof.

12. The capacitor structure of claim 11 wherein the demarcation between the upper and lower portions is located about 5-10 nm from the bottom surface of the capacitor dielectric layer.

13. The capacitor structure of claim 10 wherein the dielectric layer comprises a thickness sufficient to prevent shorting of the capacitor electrodes.

14. A capacitor structure comprising:

a capacitor including

a top electrode,

a bottom electrode,

a capacitor dielectric layer between the top and bottom electrodes,

wherein the capacitor includes an upper and a lower portion, the upper and lower portion whose demarcation is between top and bottom surfaces of the capacitor dielectric layer, the demarcation between the upper and lower portions of the capacitors prevent shorting of the electrodes by conductive fence which can form during processing, wherein the demarcation between the upper and lower portions is located at least 3 nm from the top and bottom surfaces of the capacitor dielectric layer; and

a dielectric sidewall spacer covering capacitor sidewalls in the upper portion of the capacitor, wherein the dielectric layer comprises a thickness sufficient to prevent shorting of the capacitor electrodes, the dielectric sidewall spacer comprises a dielectric material selected from the group comprising oxides, nitrides, aluminum oxide or combination thereof.

15. The capacitor structure of claim 14 wherein the demarcation between the upper and lower portions is located about 5-10 nm from the bottom surface of the capacitor dielectric layer.

16. The capacitor structure of claim 7 wherein the dielectric layer comprises a thickness sufficient to prevent shorting of the capacitor electrodes.

17. A capacitor structure comprising:

a capacitor including

a top electrode,

a bottom electrode,

a capacitor dielectric layer between the top and bottom electrodes,

wherein the capacitor includes an upper and a lower portion, the upper and lower portion whose demarcation is between top and bottom surfaces of the capacitor dielectric layer, the demarcation between the upper and lower portions of the capacitors prevent shorting of the electrodes by conductive fence which can form during processing, wherein the demarcation between the upper and lower portions is located at least 3 nm from the bottom surface of the capacitor dielectric layer; and

a dielectric sidewall spacer covering capacitor sidewalls in the upper portion of the capacitor, the dielectric layer comprises a thickness sufficient to prevent shorting of the capacitor electrodes.

18. The capacitor structure of claim 17 wherein the demarcation between the upper and lower portions is located about 5-10 nm from the bottom surface of the capacitor dielectric layer.

19. The capacitor structure of claim 7 wherein the demarcation between the upper and lower portions is at least 3 nm from the bottom surface of the capacitor dielectric layer.

20. The capacitor structure of claim 10 wherein the demarcation between the upper and lower portions is at least 3 nm from the bottom surface of the capacitor dielectric layer.

21. The capacitor structure of claim 13 wherein the demarcation between the upper and lower portions is at least 3 nm from the bottom surface of the capacitor dielectric layer.

22. The capacitor structure of claim 16 wherein the demarcation between the upper and lower portions is at least 3 nm from the bottom surface of the capacitor dielectric layer.