Semiconductor device with double sidewall spacer and layered contact
View Patent ↗A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silicon nitride film is formed on the gate electrode. A silicon oxide film is formed on a side surface of the gate electrode. A second silicon nitride film is partially formed on the silicon layer and on a side surface of the silicon oxide film. A conductive layer is formed on the silicon layer.
1. A semiconductor device having a pair of impurity regions in a semiconductor substrate, comprising:
a gate insulating film which is formed between the impurity regions;
a gate electrode which is formed on the gate insulating film;
a first silicon nitride film which is formed on the gate electrode;
a sidewall which is formed only by a silicon oxide film so as to reach to a surface of the semiconductor substrate and which is formed on a side surface of the gate electrode;
a silicon layer which is selectively formed on the impurity region so as to contact with a surface of the sidewall;
a second silicon nitride film which is formed partially on the silicon layer and partially on a side surface of the silicon oxide film; and
a conductive layer which is formed on the silicon layer, the first silicon nitride film, and the second silicon nitride film, a conductive film being formed between said conductive layer and said first silicon nitride film.
2. A device as claimed in claim 1 , wherein:
the gate electrode is made of a polysilicon layer and a metal layer or a metal silicide layer.
3. A device as claimed in claim 1 , wherein:
the silicon oxide film and the second silicon nitride film constitute a double sidewall spacer.
4. A device as claimed in claim 3 , wherein:
the silicon layer is insulated from the gate electrode only by the silicon oxide film at a lower portion of the gate electrode, and
the conductive layer is insulated from the gate electrode by the double sidewall spacer at an upper portion of the gate electrode.
5. A device as claimed in claim 1 , wherein:
a silicide layer is formed between the conductive layer and the silicon layer, and in contact with the silicon layer.
6. A device as claimed in claim 1 , wherein:
a titanium silicide layer is formed between the conductive layer and the silicon layer, and is in contact with the silicon layer.
7. A device as claimed in claim 6 , wherein:
a depletion layer is formed near the impurity region so that the silicon layer prevents the depletion layer from reaching the titanium silicide layer.
8. A device as claimed in claim 1 , wherein:
no silicon nitride film is present near a region where the gate electrode and the impurity region are adjacent to each other.