Method of etching a layer in a trench and method of fabricating a trench capacitor
View Patent ↗To fabricate a trench capacitor in a substrate, a trench is formed in the substrate. The trench has an upper region and a lower region. In the trench, first of all nanocrystallites and/or a seed layer for nanocrystallites are deposited in the upper region and the lower region. Then, the nanocrystallites and/or the seed layer are removed from the upper region of the trench by means of an etching process. The etching parameters of the etching process are selected in such a way that the seed layer and/or the nanocrystallites which are uncovered in the upper region and the lower region are removed only from the upper region. Consequently, an expensive mask layer can be avoided in the lower region of the trench.
1. A method for fabricating a trench capacitor having an inner capacitor electrode and an outer capacitor electrode, which comprises the following method steps:
providing a substrate having a substrate surface and a trench formed therein, the trench having a trench sidewall, an upper region proximal to the substrate surface and a lower region distal from the substrate surface;
forming a stop layer on the trench sidewall;
depositing nanocrystallites on the stop layer to form a part of the outer capacitor electrode;
subjecting the nanocrystallites to a dry-etching process, with the nanocrystallites exposed in the upper region and in the lower region of the trench, to partly remove the nanocrystallites from the trench, and thereby setting parameters for the dry-etching process causing the nanocrystallites to be removed from the upper region of the trench but to remain in place in the lower region of the trench, the dry-etching process including etching with sulfur hexafluoride and nitrogen as etching gases; and
subsequently forming a capacitor dielectric in the trench; and
at least partially filling the trench with a conductive trench filling forming the inner capacitor electrode.
2. The method according to claim 1 , which comprises forming the stop layer on the sidewall in the lower region and in the upper region of the trench.
3. The method according to claim 1 , which comprises setting an etching time of the dry-etching process as a parameter.
4. The method according to claim 1 , which comprises stopping the etching process at the stop layer to protect the trench sidewall.
5. The method according to claim 1 , which comprises depositing an amorphous layer on the nanocrystallites.
6. The method according to claim 1 , wherein the dry-etching process comprises etching at a pressure of between 3.9 Pa and 6.8 Pa in the etching chamber.
7. The method according to claim 1 , which comprises forming an insulation collar on the trench sidewall in the upper region.
8. The method according to claim 1 , wherein the dry-etching process comprises introducing a power of between 100 W and 400 W into a process chamber during the etching process.
9. The method according to claim 1 , wherein the dry-etching process comprises etching for a time of between 5 seconds and 300 seconds.
10. A method of fabricating a trench capacitor having an inner capacitor electrode and an outer capacitor electrode, which comprises the following method steps:
providing a substrate having a substrate surface and a trench formed therein, the trench having a trench sidewall, an upper region proximal to the substrate surface and a lower region distal from the substrate surface;
forming a stop layer on the trench sidewall;
forming a seed layer on the stop layer in the lower region and in the upper region of the trench;
subjecting the seed layer to a dry-etching process, while the seed layer is exposed in the upper region and in the lower region, to partly remove the layer from the trench, and thereby setting the parameters for the dry-etching process such that the seed layer is removed from the upper region of the trench but remains in place in the lower region of the trench;
selectively depositing a layer of nanocrystallites, to form a part of the outer capacitor electrode;
forming a capacitor dielectric in the trench; and
at least partially filling the trench with a conductive trench filling to form the inner capacitor electrode.
11. The method according to claim 10 , wherein the depositing step comprises forming the nanocrystallites on the seed layer in the lower region of the trench.
12. The method according to claim 10 , which comprises forming the stop layer in the lower region and the upper region of the trench.
13. The method according to claim 10 , which comprises stopping the etching process at the stop layer to protect the trench sidewall.
14. The method according to claim 10 , which comprises depositing an amorphous layer on the nanocrystallites.
15. The method according to claim 10 , wherein the dry-etching process comprises etching with sulfur hexafluoride and nitrogen as etching gases, and setting a gas-flow rate ratio of sulfur hexafluoride to nitrogen at between 0.1 and 1.
16. The method according to claim 10 , wherein the dry-etching process comprises etching at a pressure of between 3.9 Pa and 6.8 Pa in the etching chamber.
17. The method according to claim 10 , which comprises forming an insulation collar on the trench sidewall in the upper region.
18. The method according to claim 10 , wherein the dry-etching process comprises introducing a power of between 100 W and 400 W into a process chamber during the etching process.
19. The method according to claim 10 , wherein the dry-etching process comprises etching for a time of between 5 seconds and 300 seconds.
20. The method according to claim 1 , wherein the dry-ecthing process comprises setting a gas-flow rate ratio of sulfur hexafluoride to nitrogen at between 0.1 and 1.